Search results for "built-in-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
49	Chengying Mao, Yansheng Lu, Jinlong Zhang	Regression testing for component-based software via built-in test design.	SAC	2007	DBLP DOI BibTeX RDF	built-in test design, method call graph, component, regression testing, test case selection
41	Jonathan Vincent, Graham King, Peter Lay, John Kinghorn	Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	continuous test, component based software engineering, built-in-test, verification and validation
33	Donghoon Han, Abhijit Chatterjee	Robust Built-In Test of RF ICs Using Envelope Detectors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
33	Qi Wang, Mani Soma	RF Front-end System Gain and Linearity Built-in Test.	VTS	2006	DBLP DOI BibTeX RDF	CMOS RF amplitude detector, gfain measurement, linearity measurement, built-in test, RF test
33	Irith Pomeranz, Sudhakar M. Reddy	Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	built-in test generation, synchronous sequential circuits, at-speed testing
33	Yingxu Wang 0001, Dilip Patel, Graham King, Ian Court, Geoff Staples, Margaret Ross 0001, Mohamed Fayad	On built-in test reuse in object-oriented framework design.	ACM Comput. Surv.	2000	DBLP DOI BibTeX RDF	frameowrk, framework reuse, test reuse, testable software, software engineering, pattern, built-in test, object-oriented technology, code reuse
31	Soumendu Bhattacharya, Abhijit Chatterjee	Use of Embedded Sensors for Built-In-Test of RF Circuits.	ITC	2004	DBLP DOI BibTeX RDF
31	Irith Pomeranz, Sudhakar M. Reddy	Built-in test generation for synchronous sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	comparison units, built-in self-test, synchronous sequential circuits, at-speed test
31	Kazumi Hatayama, Michinobu Nakao, Yasuo Sato	At-Speed Built-in Test for Logic Circuits with Multiple Clocks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
30	Irith Pomeranz, Sudhakar M. Reddy	A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	scan circuits, Built-in testing, Cartesian product
30	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
29	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
29	Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian	A Test Interface for Built-In Test of Non-Isolated Scanned Cores.	VTS	2003	DBLP DOI BibTeX RDF
29	Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich	An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.	ETS	2007	DBLP DOI BibTeX RDF
28	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.	DFT	2006	DBLP DOI BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
26	Taewoong Jeon, Hyonwoo Seung, Sungyoung Lee	Embedding built-in tests in hot spots of an object-oriented framework.	ACM SIGPLAN Notices	2002	DBLP DOI BibTeX RDF	hook classes, testability, object-oriented framework, built-in test (BIT)
25	Achintya Halder, Abhijit Chatterjee	Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
24	Dimitrios Kagaris, Spyros Tragoudas	A multiseed counter TPG with performance guarantee.	ICCD	1996	DBLP DOI BibTeX RDF	built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation
23	Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama	Built-in self test for C-testable ILA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
23	Wolfgang O. Budde	Modular testprocessor for VLSI chips and high-density PC boards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo	Application of High-Quality Built-In Test to Industrial Designs.	ITC	2002	DBLP DOI BibTeX RDF
23	Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham	Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors.	VTS	2008	DBLP DOI BibTeX RDF	Amplitude detector, RF detector, RF receiver, Built-in test, RF test
23	Yingxu Wang 0001, Graham King, Hakan Wickburg	A Method for Built-in Tests in Component-based Software Maintenance.	CSMR	1999	DBLP DOI BibTeX RDF	maintenance mode, normal mode, test component reuse, reengineering maintenance, Software engineering, software maintenance, software components, built-in test
22	Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham	Built-In Test of RF Mixers Using RF Amplitude Detectors.	ISQED	2007	DBLP DOI BibTeX RDF
22	Franck Barbier, Nicolas Belloir	Component Behavior Prediction and Monitoring through Built-In Test.	ECBS	2003	DBLP DOI BibTeX RDF
21	Matthias Merdes, Rainer Malaka, Dima Suliman, Barbara Paech, Daniel Brenner, Colin Atkinson 0001	Ubiquitous RATs: how resource-aware run-time tests can improve ubiquitous software systems.	SEM	2006	DBLP DOI BibTeX RDF	MORABIT, resource-aware test (RAT), run-time testing, ubiquitous software, built-in test (BIT)
21	Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu	Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.	3DIC	2015	DBLP DOI BibTeX RDF
21	Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich	Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.	DDECS	2007	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.	DAC	1999	DBLP DOI BibTeX RDF
21	Ting-Ting Y. Lin, Huoy-Yu Liou	A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
21	Magdy S. Abadir, Melvin A. Breuer	Test Schedules for VLSI Circuits Having Built-In Test Hardware.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	testable design methodology, testing, pipelining, Design for testability, test schedules, test plans
21	Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham	Design of Test Pattern Generators for Built-In Test.	ITC	1984	DBLP BibTeX RDF
20	Dongchao Ji, Bifeng Song, Fei Han	An Improved KNN Algorithm of Intelligent Built-in Test.	ICNSC	2008	DBLP DOI BibTeX RDF
17	Daniel Brenner, Colin Atkinson 0001, Rainer Malaka, Matthias Merdes, Barbara Paech, Dima Suliman	Reducing verification effort in component-based software engineering through built-in testing.	Inf. Syst. Frontiers	2007	DBLP DOI BibTeX RDF	Run-time testing, MORABIT, Built-in test, Integration test
17	Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio	On-Chip Testing Techniques for RF Wireless Transceivers.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	Wireless Transceivers, Loop-back test, Built-in test, RF test
17	Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil	X-Tolerant Test Response Compaction.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Testability, Built-In Test, VLSI Test
17	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
17	James W. Watterson, Jill J. Hallenbeck	Modulo 3 Residue Checker: New Results on Performance and Cost.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage
17	Wilfried Daehn, Joachim Mucha	A Hardware Approach to Self-Testing of Large Programmable Logic Arrays.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	programmable logic array (PLA), Built-in test, pattern generation, nonlinear feedback shift registers
17	Edward J. McCluskey, Saied Bozorgui-Nesbat	Design for Autonomous Test.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	CMOS testing, partitioning, design for testability, test pattern generation, self-test, Built-in test, signature analysis, VLSI testing, stuck- open faults, exhaustive testing
17	Norman Benowitz, Donald F. Calhoun, Gary E. Alderson, John E. Bauer, Carl T. Joeckel	An Advanced Fault Isolation System for Digital Logic.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	large-scale integration (LSI) testing, subsystem test, self test, built-in test (BIT), Automatic test equipment (ATE), fault isolation, system maintenance, test response
16	Selim Sermet Akbay, Abhijit Chatterjee	Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference.	VTS	2004	DBLP DOI BibTeX RDF
16	Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik	Alternative Test Methods Using IEEE 1149.4.	DATE	2000	DBLP DOI BibTeX RDF
16	Congzhi Huang, Yang Yang	IFCN-BIASN Based Built-In Test Signal State Recognition for Heavy-Duty Gas Turbine Controller.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
16	Fei Guan, Wei-Wei Cui, Lian-Feng Li, Weikang Xue, Xiaodong Ma, Dongpao Hong	A Method of False Alarm Recognition in Built-in Test Considering Its Time Series Characteristics.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
16	Congzhi Huang, Yasong Wang, Guolian Hou, Jianhua Zhang 0007	An LSTM-BINN Approach for Built-In Test Analog Signal State Recognition of Heavy-Duty Gas Turbine Controllers.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
16	Junyou Shi, Qingjie He, Zili Wang	Integrated Stateflow-based simulation modelling and testability evaluation for electronic built-in-test (BIT) systems.	Reliab. Eng. Syst. Saf.	2020	DBLP DOI BibTeX RDF
16	Konstantinos Poulos, Themistoklis Haniotakis	A Built In Test circuit for waveform classification at high frequencies.	NATW	2020	DBLP DOI BibTeX RDF
16	Irith Pomeranz	Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests.	IOLTS	2020	DBLP DOI BibTeX RDF
16	Matthias Kampmann, Michael A. Kochte, Chang Liu 0010, Eric Schneider, Sybille Hellebrand, Hans-Joachim Wunderlich	Built-In Test for Hidden Delay Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
16	Thomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee	Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
16	Badi Guibane, Belgacem Hamdi, Brahim Bensalem, Abdellatif Mtibaa	A novel efficient TSV built-in test for stacked 3D ICs.	Turkish J. Electr. Eng. Comput. Sci.	2018	DBLP DOI BibTeX RDF
16	Jun-Yang Lei, Thomas Moon, Justin Chow, Suresh K. Sitaraman, Abhijit Chatterjee	A Monobit Built-In Test and Diagnostic System for Flexible Electronic Interconnect.	ATS	2018	DBLP DOI BibTeX RDF
16	Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee	Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
16	Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu	Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.	ATS	2017	DBLP DOI BibTeX RDF
16	Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee	Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization.	ITC	2017	DBLP DOI BibTeX RDF
16	Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth	A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.	IEICE Trans. Inf. Syst.	2016	DBLP DOI BibTeX RDF
16	Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld	Built-in test of millimeter-Wave circuits based on non-intrusive sensors.	DATE	2016	DBLP BibTeX RDF
16	Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld	Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
16	Li Xu 0006, Marvin Onabajo	A low-power temperature-compensated relaxation oscillator for built-in test signal generation.	MWSCAS	2015	DBLP DOI BibTeX RDF
16	Xian Wang 0003, Kenfack Blanchard, Estella Silva, Abhijit Chatterjee	"Safe" built-in test and tuning of boost converters using feedback loop perturbations.	LATS	2015	DBLP DOI BibTeX RDF
16	Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir	Low-cost EVM built-in test of RF transceivers.	IDT	2014	DBLP DOI BibTeX RDF
16	Xian Wang 0003, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee	Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
16	Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir	True non-intrusive sensors for RF built-in test.	ITC	2013	DBLP DOI BibTeX RDF
16	Miao Zhang 0001, Yi Shen 0001, Xiao-Lei Zhang 0003, Zhi-Bo Wang, Ye Zhang 0008	Built-in Test Signal Feature Extraction Method Based on Hilbert-Huang Transform.	Adv. Data Sci. Adapt. Anal.	2012	DBLP DOI BibTeX RDF
16	Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma	Experiences with non-intrusive sensors for RF built-in test.	ITC	2012	DBLP DOI BibTeX RDF
16	Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda	Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications.	J. Electron. Test.	2011	DBLP DOI BibTeX RDF
16	Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume	A built-in test circuit for open defects at interconnects between dies in 3D ICs.	3DIC	2011	DBLP DOI BibTeX RDF
16	Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas	A Built-In-Test Circuit for RF Differential Low Noise Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
16	Wimol San-Um, Masayoshi Tachibana	A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration.	ISCAS	2010	DBLP DOI BibTeX RDF
16	Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio	An On-Chip Loopback Block for RF Transceiver Built-In Test.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
16	Qais Al-Gayem, Hongyuan Liu 0001, Andrew Richardson 0001, Nick Burd	Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems.	ETS	2009	DBLP DOI BibTeX RDF	bio-fluidics, MNT, self-test, microfluidics, embedded test
16	Vishwanath Natarajan, Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee	Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems.	VLSI Design	2008	DBLP DOI BibTeX RDF
16	Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio	A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
16	Rajarajan Senguttuvan, Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee	Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters.	ETS	2008	DBLP DOI BibTeX RDF
16	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
16	Guoyan Zhang, Ronan Farrell	Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits.	DDECS	2006	DBLP DOI BibTeX RDF
16	Guoyan Zhang, Ronan Farrell	An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits.	ICECS	2006	DBLP DOI BibTeX RDF
16	Zhen Liu, Hui Lin, Xin (Robert) Luo	Intelligent Built-in Test (BIT) for More-Electric Aircraft Power System Based on Hybrid Generalized LVQ Neural Network.	ISNN (2)	2006	DBLP DOI BibTeX RDF
16	An Sang Hou	A built-in-test scheme for evaluating the parameters of floating-gate MOS transistors.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
16	Karen Taylor, Bryan Nelson, Alan Chong, Henry C. Lin, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz	Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
16	John W. Sheppard, Mark A. Kaufman	A Bayesian approach to diagnosis and prognosis using built-in test.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
16	Robert W. Gao	Guest Editorial Special Section on Built-In-Test.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
16	Selim Sermet Akbay, Abhijit Chatterjee	Built-In Test of RF Components Using Mapped Feature Extraction Sensors.	VTS	2005	DBLP DOI BibTeX RDF
16	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
16	Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz	CMOS Built-In Test Architecture for High-Speed Jitter Measurement.	ITC	2003	DBLP DOI BibTeX RDF
16	Yingxu Wang 0001, Shushma Patel, Dilip Patel	On Built-in Test Classes for Object-Oriented and Component-Based Information Systems.	OOIS	2001	DBLP DOI BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.	ICCD	2001	DBLP DOI BibTeX RDF
16	Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski	Built-in Test of Analog Non-Linear Circuits in a SOC Environment.	VLSI-SOC	2001	DBLP BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits.	ETW	2000	DBLP DOI BibTeX RDF
16	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.	VTS	1999	DBLP DOI BibTeX RDF
16	Krishnendu Chakrabarty, Brian T. Murray	Design of built-in test generator circuits using width compression.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	Improved built-in test pattern generators based on comparison units for synchronous sequential circuits.	ICCD	1998	DBLP DOI BibTeX RDF
16	Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois	Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
16	Colin M. Maunder	A Universal Framework for Managed Built-in Test.	ITC	1993	DBLP DOI BibTeX RDF
16	Michael Zimmermann, Manfred Geilert	Generation of embedded RAMs with built-in test using object-oriented programming.	EURO-DAC	1990	DBLP DOI BibTeX RDF
16	Fevzi Belli, Ismael Camara, Alfred Schmidt	A Built-in Test Language for PROLOG to Validate Knowledge-Based Systems.	IEA/AIE (Vol. 2)	1990	DBLP DOI BibTeX RDF	Prolog
16	Colin Maunder	Built-in test for VLSI - pseudorandom techniques: Bardell, P H, McArney, W H and Savir, J Wiley, New York, NY, USA (1987) £45.00 pp 354.	Microprocess. Microsystems	1989	DBLP DOI BibTeX RDF