Search results for "cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau	Reducing memory latency using a small software driven array cache.	HICSS (1)	1995	DBLP DOI BibTeX RDF	small software driven array cache, data references, array reference, nonarray reference, data cache designs, cache space, cache control mechanisms, array references, data cache performance, hardware driven data prefetching scheme, software driven cache design, array cache, low runtime overhead, performance evaluation, data structures, compiler, programming, programming, prefetching, program compilers, cache storage, cache performance, temporal locality, spatial locality, memory latency
108	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
108	Lars Arge, Michael A. Bender, Erik D. Demaine, Charles E. Leiserson, Kurt Mehlhorn	04301 Abstracts Collection - Cache-Oblivious and Cache-Aware Algorithms.	Cache-Oblivious and Cache-Aware Algorithms	2004	DBLP BibTeX RDF
104	Frank Mueller 0001, David B. Whalley	Fast instruction cache analysis via static cache simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	instruction cache analysis, static cache simulation, cache configuration, instruction reference, cache hit, counter incrementation, code execution frequency, local state information updating, frequency counters, program exit, virtual machines, cache storage, program diagnostics, dynamic simulation, cache miss
100	Kashif Ali, Mokhtar Aboelaze, Suprakash Datta	Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
100	Prateek Pujara, Aneesh Aggarwal	Increasing cache capacity through word filtering.	ICS	2007	DBLP DOI BibTeX RDF	cache capacity, cache compression, cache noise, cache organization, cache miss rate
97	Yiming Hu, Tycho Nightingale, Qing Yang 0001	RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage Systems.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	fault-tolerance, performance, reliability, storage systems, disks
96	Mazen Kharbutli, Yan Solihin	Counter-Based Cache Replacement and Bypassing Algorithms.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cache Bypassing, Counter-Based Algorithms, Cache memories, Cache Replacement, Cache Misses
93	Prateek Pujara, Aneesh Aggarwal	Increasing the cache efficiency by eliminating noise.	HPCA	2006	DBLP DOI BibTeX RDF
93	Xavier Vera, Björn Lisper, Jingling Xue	Data cache locking for tight timing calculations.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	data cache analysis, embedded systems, Worst-case execution time, safety critical systems
92	Lars Arge, Michael A. Bender, Erik D. Demaine, Charles E. Leiserson, Kurt Mehlhorn (eds.)	Cache-Oblivious and Cache-Aware Algorithms, 18.07. - 23.07.2004	Cache-Oblivious and Cache-Aware Algorithms	2005	DBLP BibTeX RDF
92	Lars Arge, Mark de Berg, Herman J. Haverkort, Ke Yi 0001	The Priority R-Tree: A Practically Efficient and Worst-Case-Optimal R-Tree.	Cache-Oblivious and Cache-Aware Algorithms	2004	DBLP BibTeX RDF
92	Joachim Gudmundsson, Jan Vahrenhold	A Simple Algorithm for I/O-efficiently Pruning Dense Spanners.	Cache-Oblivious and Cache-Aware Algorithms	2004	DBLP BibTeX RDF
89	Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia	Compression in cache design.	ICS	2007	DBLP DOI BibTeX RDF	cache compression, prefetching, cache design
89	Rui Min, Wen-Ben Jone, Yiming Hu	Location cache: a low-power L2 cache system.	ISLPED	2004	DBLP DOI BibTeX RDF	L1/L2 caches, data location, power, TLB, set-associative caches
89	Chih-Yung Chang, Jang-Ping Sheu, Hsi-Chiuen Chen	Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping.	ICPADS	2000	DBLP DOI BibTeX RDF	array padding, multi-level cache, cache partitioning, loop tiling, direct mapping, cache conflict
85	Yiming Hu, Qing Yang 0001, Tycho Nightingale	RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems.	HPCA	1999	DBLP DOI BibTeX RDF
85	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
81	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
81	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
81	Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu	Run-Time Cache Bypassing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache bypassing, Data cache, cache management, temporal locality, spatial locality
77	Sungjune Youn, Hyunhee Kim, Jihong Kim 0001	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
77	Xinhua Tian, Minxuan Zhang	A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching.	ICESS	2007	DBLP DOI BibTeX RDF
77	Jih-Fu Tu	Cache Management for Discrete Processor Architectures.	ISPA	2005	DBLP DOI BibTeX RDF	Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency
73	Paul Racunas, Yale N. Patt	Partitioned first-level cache design for clustered microarchitectures.	ICS	2003	DBLP DOI BibTeX RDF	partitioned cache, clustered microarchitecture
73	Chia-Lin Yang, Chien-Hao Lee	HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, instruction cache
70	Tao Li 0006, Lizy K. John	OS-aware tuning: improving instruction cache energy efficiency on system workloads.	IPCCC	2006	DBLP DOI BibTeX RDF
70	Zhiwen Xu, Xiaoxin Guo, Zhengxuan Wang, Yunjie Pang	The Dynamic Cache Algorithm of Proxy for Streaming Media.	ICIC (1)	2005	DBLP DOI BibTeX RDF
70	Allan Hartstein, Viji Srinivasan, Thomas R. Puzak, Philip G. Emma	Cache miss behavior: is it sqrt(2)?	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	performance, memory hierarchy, cache organization
70	Muhamed F. Mudawar	Scalable cache memory design for large-scale SMT architectures.	WMPI	2004	DBLP DOI BibTeX RDF	scalable multiported cache memory, simultaneous multithreaded architectures
70	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar	Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay.	HPCA	2002	DBLP DOI BibTeX RDF	resizable cache design, low power processor, energy aware architecture
70	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Trace Cache Redundancy: Red & Blue Traces.	HPCA	2000	DBLP DOI BibTeX RDF	trace cache, instruction fetch, code reordering
69	Aneesh Aggarwal	Reducing latencies of pipelined cache accesses through set prediction.	ICS	2005	DBLP DOI BibTeX RDF	instructions per cycle, line prediction, set prediction, speculative cache access, cache memory
69	Mirza Omer Beg, Peter van Beek	A graph theoretic approach to cache-conscious placement of data for direct mapped caches.	ISMM	2010	DBLP DOI BibTeX RDF	cache consciousness, data placement in cache, offline algorithms, memory management, cache optimization
69	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
69	Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou	Deconstructing new cache designs for thwarting software cache-based side channel attacks.	CSAW	2008	DBLP DOI BibTeX RDF	microarchitectural analysis, cryptanalysis, side-channel analysis, timing attack, cache architecture, cache attack
69	José V. Busquets-Mataix, Juan José Serrano	The impact of extrinsic cache performance on predictability of real-time systems.	RTCSA	1995	DBLP DOI BibTeX RDF	tighter bounds, cached programs, extrinsic cache behavior, inter-task cache interference, cache predictability, performance evaluation, real-time systems, real-time systems, predictability, worst case execution time, schedulability analysis, cache storage, cache performance
66	Julien Dusser, Thomas Piquet, André Seznec	Zero-content augmented caches.	ICS	2009	DBLP DOI BibTeX RDF	null block, zero block, cache, compression
66	Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black	Avoiding Initialization Misses to the Heap.	ISCA	2002	DBLP DOI BibTeX RDF	invalid memory traffic, initializing stores, cache installation, allocation range cache
66	Prateek Pujara, Aneesh Aggarwal	Cache Noise Prediction.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
66	Moinuddin K. Qureshi, Yale N. Patt	Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches.	MICRO	2006	DBLP DOI BibTeX RDF
66	Jung-Wook Park, Cheong-Ghil Kim, Jung-Hoon Lee, Shin-Dug Kim	An energy efficient cache memory architecture for embedded systems.	SAC	2004	DBLP DOI BibTeX RDF	selective way access, skewed associativity, embedded system, memory hierarchy, low power cache
66	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	A first look at the interplay of code reordering and configurable caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cache exploration, code reorganization, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache, code layout, code reordering
66	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Automatic Tuning of Two-Level Caches to Embedded Applications.	DATE	2004	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache
66	Junho Shim, Peter Scheuermann, Radek Vingralek	Proxy Cache Algorithms: Design, Implementation, and Performance.	IEEE Trans. Knowl. Data Eng.	1999	DBLP DOI BibTeX RDF	World Wide Web, caching, Proxy, cache replacement, cache consistency
66	Xingyan Tian, Kejia Zhao, Huowang Chen, Hongyan Du	Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
66	Trishul M. Chilimbi, Mark D. Hill, James R. Larus	Cache-Conscious Structure Layout.	PLDI	1999	DBLP DOI BibTeX RDF	cache-conscious allocation, cache-conscious data placement, cache-conscious reorganization, clustering, coloring
66	Li Zhao 0002, Ravi R. Iyer 0001, Srihari Makineni, Don Newell, Liqun Cheng	NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cache, directory
66	Zhenghong Wang, Ruby B. Lee	New cache designs for thwarting software cache-based side channel attacks.	ISCA	2007	DBLP DOI BibTeX RDF	security, cache, computer architecture, processor, timing attacks, side channel
66	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP DOI BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
65	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
65	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
65	Wei Zhang 0002	Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	write-back cache, in-cache replication, Soft error
62	Pepijn J. de Langen, Ben H. H. Juurlink	Reducing traffic generated by conflict misses in caches.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	caches, embedded processors, power reduction, conflict misses
62	Sung-Hoon Shim, Cheol Hong Kim, Jong Wook Kwak, Chu Shik Jhon	Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor.	EUC	2004	DBLP DOI BibTeX RDF
62	Aamer Jaleel, Matthew Mattina, Bruce L. Jacob	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.	HPCA	2006	DBLP DOI BibTeX RDF
62	Prateek Pujara, Aneesh Aggarwal	Restrictive Compression Techniques to Increase Level 1 Cache Capacity.	ICCD	2005	DBLP DOI BibTeX RDF
62	Andrea Santoro, Bruno Ciciani, Francesco Quaglia, Michele Colajanni	Two-Tier Cooperation: A Scalable Protocol for Web Cache Sharing.	NCA	2001	DBLP DOI BibTeX RDF
62	Roni Rosner, Avi Mendelson, Ronny Ronen	Filtering Techniques to Improve Trace-Cache Efficiency.	IEEE PACT	2001	DBLP DOI BibTeX RDF
62	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multi-function computing cache architecture.	FPGA	2000	DBLP DOI BibTeX RDF
62	Javier Lira, Carlos Molina, Antonio González 0001	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
62	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
62	Jaume Abella 0001, Antonio González 0001	Heterogeneous way-size cache.	ICS	2006	DBLP DOI BibTeX RDF	adaptive, low power, cache memories, set-associative
62	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
62	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A Highly-Configurable Cache Architecture for Embedded Systems.	ISCA	2003	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, low energy, architecture tuning
62	Trishul M. Chilimbi, Bob Davidson, James R. Larus	Cache-Conscious Structure Definition.	PLDI	1999	DBLP DOI BibTeX RDF	cache-conscious definition, class splitting, field reorganization, structure splitting, Java
62	Yun Liang 0001, Tulika Mitra	Instruction cache locking using temporal reuse profile.	DAC	2010	DBLP DOI BibTeX RDF	cache locking, temporal reuse profile, cache
62	Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John	Modeling and Analysis of The Difference-Bit Cache.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	hit access time, cache mapping strategies*, Cache memory, critical path
62	Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King	Performance of Shared Cache on Multithreaded Architectures.	PDP	1996	DBLP DOI BibTeX RDF	shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache
62	Bob Janssens, W. Kent Fuchs	The Performance of Cache-Based Error Recovery in Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	cache-based error recovery performance, cache-based checkpointing, rollback error recovery, shared-memorymultiprocessors, inherent redundancy, computation state, rollback propagation, EncoreMultimax, recovery schemes, cache-based schemes, low performance overhead, checkpoint interval, performance evaluation, performance evaluation, virtual machines, multiprocessors, redundancy, memory hierarchy, shared memory systems, system recovery, buffer storage, parallel applications, cache coherence protocol, transient errors, cache replacement policy, address traces
62	Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany	Improving data cache performance with integrated use of split caches, victim cache and stream buffers.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	array cache, memory access time, scalar cache, victim cache, stream buffer
62	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Fast configurable-cache tuning with a unified second-level cache.	ISLPED	2005	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache
58	Yang Xiao 0001, Hui Chen 0001	Optimal Callback with Two-Level Adaptation for Wireless Data Access.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	wireless data access, Adaptive, cache, strong consistency, callback
58	Murthy Durbhakula	Sharing-aware OS scheduling algorithms for multi-socket multi-core servers.	IFMT	2008	DBLP DOI BibTeX RDF	cache-to-cache transfers, scheduling algorithms
58	Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez	Procedure placement using temporal-ordering information: dealing with code size expansion.	CASES	2004	DBLP DOI BibTeX RDF	min-matching, profiling, instruction cache, Hamiltonian-path, cache miss, code size, code placement
58	Charles E. Leiserson	Cache-Oblivious Algorithms.	CIAC	2003	DBLP DOI BibTeX RDF
58	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
58	Matteo Frigo, Charles E. Leiserson, Harald Prokop, Sridhar Ramachandran	Cache-Oblivious Algorithms.	FOCS	1999	DBLP DOI BibTeX RDF
58	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis	Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.	ICCD	1999	DBLP DOI BibTeX RDF
58	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Brief announcement: low depth cache-oblivious sorting.	SPAA	2009	DBLP DOI BibTeX RDF	schedulers, parallel algorithms, multiprocessors, sorting, merging, cache-oblivious algorithms
58	Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	A predictive decode filter cache for reducing power consumption in embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Cache, embedded processors, power optimization
58	Fengguang Song, Shirley Moore, Jack J. Dongarra	L2 Cache Modeling for Scientific Applications on Chip Multi-Processors.	ICPP	2007	DBLP DOI BibTeX RDF	cache performance modeling, architecture, chip multi-processor, multi-threaded programming
58	Jie Tao 0001, Wolfgang Karl	Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities.	VALUETOOLS	2006	DBLP DOI BibTeX RDF	code optimization, performance visualization, cache simulation
58	Keun Soo Yim, Jang-Soo Lee, Jihong Kim 0001, Shin-Dug Kim, Kern Koh	A Space-Efficient On-Chip Compressed Cache Organization for High Performance Computing.	ISPA	2004	DBLP DOI BibTeX RDF	processor-memory performance gap, on-chip compressed cache, fine-grained management, internal fragmentation problem, Parallel processing
58	Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems	Application-adaptive intelligent cache memory system.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality
58	Somnath Ghosh, Margaret Martonosi, Sharad Malik	Cache miss equations: a compiler framework for analyzing and tuning memory behavior.	ACM Trans. Program. Lang. Syst.	1999	DBLP DOI BibTeX RDF	optimization, compilation, program transformation, cache memories
58	Guangdeng Liao, Heeyeol Yu, Laxmi N. Bhuyan	A new IP lookup cache for high performance IP routers.	DAC	2010	DBLP DOI BibTeX RDF	cache indexing, cache replacement policies, IP routers
58	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
58	Michael Behar, Avi Mendelson, Avinoam Kolodny	Trace cache sampling filter.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	cache utilization, sampling filter, power dissipation, Trace cache
58	Mazen Kharbutli, Yan Solihin, Jaejin Lee	Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Cache hashing, cache indexing, prime modulo, odd-multiplier displacement, conflict misses
58	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
58	Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski	Impact of memory hierarchy on program partitioning and scheduling.	HICSS (2)	1995	DBLP DOI BibTeX RDF	parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860
58	Matteo Frigo, Volker Strumpen	The Cache Complexity of Multithreaded Cache Oblivious Algorithms.	Theory Comput. Syst.	2009	DBLP DOI BibTeX RDF	Multithreading, Cache oblivious algorithms, Stencil computations
58	Jianwei Dai, Lei Wang 0003	Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy.	ISLPED	2009	DBLP DOI BibTeX RDF	low-power technique, way-tag array, cache
58	Rakesh Reddy, Peter Petrov	Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems.	CASES	2007	DBLP DOI BibTeX RDF	real-time embedded systems, cache interference
58	Scott D. Carson, Sanjeev Setia	Analysis of the Periodic Update Write Policy For Disk Cache.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	periodic update write policy, average access time, dirty cache blocks, disk read requests, cache-hit ratio, competing cache write policies, bulk arrivals, traffic jam effect, degraded service, write packages, scheduling, file systems, storage management, buffer storage, storage allocation, disk scheduling, data storage, computer systems, disk cache, design criteria, average response time
58	Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid	Configurable cache subsetting for fast cache tuning.	DAC	2006	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
58	Wei Zhang 0002	Enhancing data cache reliability by the addition of a small fully-associative replication cache.	ICS	2004	DBLP DOI BibTeX RDF	in-cache replication, write-back cache, soft error
58	Julio Sahuquillo, Ana Pont	The Filter Cache: A Run-Time Cache Management Approach1.	EUROMICRO	1999	DBLP DOI BibTeX RDF	multi-lateral cache, data cache management, multiprocessor systems, memory architectures, data locality
54	Jichuan Chang, Gurindar S. Sohi	Cooperative Caching for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF