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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/patmos/GoudosKNMN18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ioannis_Messaris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maria_Ntogramatzi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikolaos_Karagiorgos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sotirios_K._Goudos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Spyridon_Nikolaidis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FPATMOS.2018.8464162>
foaf:homepage <https://doi.org/10.1109/PATMOS.2018.8464162>
dc:identifier DBLP conf/patmos/GoudosKNMN18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FPATMOS.2018.8464162 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ioannis_Messaris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maria_Ntogramatzi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikolaos_Karagiorgos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sotirios_K._Goudos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Spyridon_Nikolaidis>
swrc:pages 169-176 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/patmos/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/patmos/GoudosKNMN18/dblp>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/patmos/patmos2018.html#GoudosKNMN18>
rdfs:seeAlso <https://doi.org/10.1109/PATMOS.2018.8464162>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/patmos>
dc:title Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document