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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/AliAC19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Malgorzata_Chrzanowska-Jeske>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammad_A._Ahmed>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muhammad_Ali>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2018.2880322>
foaf:homepage <https://doi.org/10.1109/TVLSI.2018.2880322>
dc:identifier DBLP journals/tvlsi/AliAC19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2018.2880322 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Malgorzata_Chrzanowska-Jeske>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammad_A._Ahmed>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muhammad_Ali>
swrc:number 3 (xsd:string)
swrc:pages 573-586 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/AliAC19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/AliAC19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#AliAC19>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2018.2880322>
dc:title Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)