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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/LinDLYCP19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bo-Heng_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jai-Ming_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Li-Yen_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Szu-Ting_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Te-Wei_Peng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/You-Lun_Deng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2018.2867833>
foaf:homepage <https://doi.org/10.1109/TVLSI.2018.2867833>
dc:identifier DBLP journals/tvlsi/LinDLYCP19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2018.2867833 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bo-Heng_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jai-Ming_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Li-Yen_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Szu-Ting_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Te-Wei_Peng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/You-Lun_Deng>
swrc:number 1 (xsd:string)
swrc:pages 57-68 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/LinDLYCP19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/LinDLYCP19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#LinDLYCP19>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2018.2867833>
dc:title Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)