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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/SimonLZA20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexandre_Levisse>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Atienza>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marina_Zapater>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/William_Andrew_Simon>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SOC46417.2020.9344087>
foaf:homepage <https://doi.org/10.1109/VLSI-SOC46417.2020.9344087>
dc:identifier DBLP conf/vlsi/SimonLZA20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SOC46417.2020.9344087 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexandre_Levisse>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Atienza>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marina_Zapater>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/William_Andrew_Simon>
swrc:pages 94-99 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/SimonLZA20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/SimonLZA20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2020.html#SimonLZA20>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SOC46417.2020.9344087>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document