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Publications at "ASYNC"( http://dblp.L3S.de/Venues/ASYNC )

URL (DBLP): http://dblp.uni-trier.de/db/conf/async

Publication years (Num. hits)
1994 (26) 1995 (23) 1996 (25) 1997 (26) 1998 (24) 1999 (22) 2000 (21) 2001 (24) 2002 (22) 2003 (22) 2004 (25) 2005 (24) 2006 (23) 2007 (19) 2008 (16) 2009 (22) 2010 (18) 2011-2012 (33) 2013 (26) 2014 (18) 2015 (21) 2016 (17) 2017 (18) 2018 (19)
Publication types (Num. hits)
inproceedings(509) proceedings(25)
Venues (Conferences, Journals, ...)
ASYNC(534)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 350 occurrences of 209 keywords

Results
Found 534 publication records. Showing 534 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Matthias Függer, Attila Kinali, Christoph Lenzen, Ben Wiederhake Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ghaith Tarawneh, Andrey Mokhov Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Christoph Hoppe, Jens Döge, Peter Reichel, Patrick Russell, Andreas Reichel, Peter Schneider A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ning Qiao, Giacomo Indiveri A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet Static Timing Analysis of Asynchronous Bundled-Data Circuits. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Florian Huemer, Andreas Steininger Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies Loihi Asynchronous Neuromorphic Research Chip. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Justin Reiher, Mark R. Greenstreet, Ian W. Jones Explaining Metastability in Real Synchronizers. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski Case Study of Process Variation-Based Domain Partitioning of GPGPUs. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland Data-Loop-Free Self-Timed Circuit Verification. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Oyinkuro Benafa, Danil Sokolov, Alex Yakovlev Loadable Kessels Counter. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018 Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  BibTeX  RDF
1Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alberto Moreno, Jordi Cortadella State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Danil Sokolov, Victor Khomenko, Alex Yakovlev, David Lloyd Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sophie Germain, Sylvain Engels, Laurent Fesquet A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sam Fok, Kwabena Boahen A Serial H-Tree Router for Two-Dimensional Arrays. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer Metastability-Aware Memory-Efficient Time-to-Digital Converters. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ameer M. S. Abdelhadi, Mark R. Greenstreet Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Alberto Moreno, Jordi Cortadella Synthesis of All-Digital Delay Lines. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Robert Najvirt, Thomas Polzer, Andreas Steininger Measuring Metastability with Free-Running Clocks. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yang Zhang 0014, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Rajit Manohar, Yoram Moses The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Maxwell Waugaman, William Koven Sharp - A Resilient Asynchronous Template. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chun-Hong Shih, Jie-Hong R. Jiang Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Johnson Fernandes, Danil Sokolov, Alex Yakovlev Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Weiwei Jiang, Steven M. Nowick A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Montek Singh, Pintian Zhang, Andrew Vitkus, Ketan Mayer-Patel, Leandra Vicci A Frameless Imaging Sensor with Asynchronous Pixels: An Architectural Evaluation. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jordi Cortadella, Alberto Moreno, Danil Sokolov, Alex Yakovlev, David Lloyd Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ghaith Tarawneh, Matthias Függer, Christoph Lenzen Metastability Tolerant Computing. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1 23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017 Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  BibTeX  RDF
1Victor Khomenko, Danil Sokolov, Andrey Mokhov, Alex Yakovlev WAITX: An Arbiter for Non-persistent Signals. Search on Bibsonomy ASYNC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside Automatic Clock: A Promising Approach toward GALSification. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sandra J. Jackson, Rajit Manohar Gradual Synchronization. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jotham Vaddaboina Manoranjan, Kenneth S. Stevens Qualifying Relative Timing Constraints for Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca 0001, Sachin S. Sapatnekar Ring Oscillator Clocks and Margins. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Christoph Lenzen, Moti Medina Efficient Metastability-Containing Gray Code 2-Sort. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andreas Steininger, Jürgen Maier 0002, Robert Najvirt The Metastable Behavior of a Schmitt-Trigger. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Benjamin Z. Tang, Frank Lane Low Power QDI Asynchronous FFT. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Suwen Yang, Frankie Y. Liu, Vincent C. Lee Asynchronously Controlled Frequency Locked Loop. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Dylan Hand, Austin Katrin, William Koven Adding Conditionality to Resilient Bundled-Data Designs. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016 Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  BibTeX  RDF
1Norman Kluge, Ralf Wollowski Optimising Bundled-Data Balsa Circuits. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Javier de San Pedro, Thomas Bourgeat, Jordi Cortadella Specification Mining for Asynchronous Controllers. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yan Peng, Ian W. Jones, Mark R. Greenstreet Finding Glitches Using Formal Methods. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Felipe A. Kuentzer, Alexandre M. Amory Fault Classification of the Error Detection Logic in the Blade Resilient Template. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Milan Babic, Steffen Zeidler 0001, Milos Krstic GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Eldar Zianbetov, Edith Beigné, Gregory di Pendina Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar Timing Driven Placement for Quasi Delay-Insensitive Circuits. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Sean Keller, Alain J. Martin, Chris Moore DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Marly Roncken, Swetha Mettala Gilla, Hoon Park, Navaneeth Jamadagni, Chris Cowan, Ivan E. Sutherland Naturalized Communication and Testing. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1L. C. Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, D. Morrissey A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jerome Cox, George Engel, David M. Zar, Ian W. Jones Synchronizers and Data Flip-Flops are Different. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Robert Najvirt, Andreas Steininger How to Synchronize a Pausible Clock to a Reference. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Danil Sokolov, Victor Khomenko, Andrey Mokhov, Alex Yakovlev, David Lloyd Design and Verification of Speed-Independent Multiphase Buck Controller. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel Blade - A Timing Violation Resilient Asynchronous Template. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Neela Lohith Penmetsa, Christos Sotiriou, Sung Kyu Lim Low Power Monolithic 3D IC Design of Asynchronous AES Core. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ben Keller, Matthew Fojtik, Brucek Khailany A Pausible Bisynchronous FIFO for GALS Systems. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang 0014, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel Performance Optimization and Analysis of Blade Designs under Delay Variability. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Andrey Mokhov, Victor Khomenko, Danil Sokolov, Alex Yakovlev Opportunistic Merge Element. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yang Zhang 0014, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel Design and Analysis of Testable Mutual Exclusion Elements. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Gabriele Miorandi, Davide Bertozzi, Steven M. Nowick Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar AES Hardware-Software Co-design in WSN. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015 Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  BibTeX  RDF
1Guangda Zhang, Jim D. Garside, Wei Song 0002, Javier Navaridas, Zhiying Wang Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Gang Wu 0002, Ankur Sharma, Chris C. N. Chu Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Rajit Manohar, Yoram Moses Analyzing Isochronic Forks with Potential Causality. Search on Bibsonomy ASYNC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Gang Wang, Xu Wang, Xinke Chen, Shuangbai Xue Test and Repair Flow for Shared BISR in Asynchronous Multi-processors. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mehrdad Najibi, Peter A. Beerel Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels Clockless Design Performance Monitoring for Nanometer Technologies. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Fu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang, Ching-Yang Huang Synthesis of QDI FSMs from Synchronous Specifications. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel Reconditioning: Automatic Power Optimization of QDI Circuits. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Graham M. Birtwistle, Kenneth S. Stevens Modelling Mixed 4phase Pipelines: Structures and Patterns. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Joycee Mekie Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Evangelia Kasapaki, Jens Sparsø Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, Luciano Lavagno Metastability in Better-Than-Worst-Case Designs. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Benjamin Z. Tang, Sunil A. Bhave, Rajit Manohar Low Power Asynchronous VLSI with NEM Relays. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Danil Sokolov, Alex Yakovlev GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014 Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  BibTeX  RDF
1Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Suwen Yang, Frankie Y. Liu Distributed Phase Correction Technique. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic, Eckhard Grass GALS Design for Spectral Peak Attenuation of Switching Current. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Reza Ramezani, Alex Yakovlev Capacitor Discharging Through Asynchronous Circuit Switching. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jonathan Tse, Andrew Lines NanoMesh: An Asynchronous Kilo-Core System-on-Chip. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Shomit Das, Vikas S. Vij, Kenneth S. Stevens SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Salomon Beer, Jerome Cox, Tom Chaney, David M. Zar MTBF Bounds for Multistage Synchronizers. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
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