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Publications of "Adit D. Singh" ( http://dblp.L3S.de/Authors/Adit_D._Singh )

URL (Homepage):  http://www.eng.auburn.edu/users/adsingh/  Author page on DBLP  Author page in RDF  Community of Adit D. Singh in ASPL-2

Publication years (Num. hits)
1987-1993 (17) 1994-1999 (15) 2001-2004 (19) 2005-2006 (20) 2007-2010 (20) 2011-2014 (21) 2015-2017 (17) 2018-2019 (7)
Publication types (Num. hits)
article(24) inproceedings(111) proceedings(1)
Venues (Conferences, Journals, ...)
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The graphs summarize 83 occurrences of 65 keywords

Results
Found 137 publication records. Showing 136 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ujjwal Guin, Wendong Wang, Charles Harper, Adit D. Singh Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. Search on Bibsonomy HOST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal Two-Pattern ∆IDDQ Test for Recycled IC Detection. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ujjwal Guin, Ziqi Zhou, Adit D. Singh Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker 0001 On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi Device aging: A reliability and security concern. Search on Bibsonomy ETS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. Search on Bibsonomy J. Electronic Testing The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker 0001 Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Bernd Becker 0001, Adit D. Singh Best paper. Search on Bibsonomy ETS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja Identifying high variability speed-limiting paths under aging. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ujjwal Guin, Ziqi Zhou, Adit D. Singh A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. Search on Bibsonomy VTS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker 0001 Efficient SAT-based generation of hazard-activated TSOF tests. Search on Bibsonomy VTS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja Exploiting path delay test generation to develop better TDF tests for small delay defects. Search on Bibsonomy ITC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Cell Aware and stuck-open tests. Search on Bibsonomy ETS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee Noise-Resilient SRAM Physically Unclonable Function Design for Security. Search on Bibsonomy ATS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Adaptive Test Methods for High IC Quality and Reliability. Search on Bibsonomy VLSI Design The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Virendra Singh, Adit D. Singh, Kewal K. Saluja A Methodology for Identifying High Timing Variability Paths in Complex Designs. Search on Bibsonomy ATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. Search on Bibsonomy ATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Scan based two-pattern tests: should they target opens instead of TDFs? Search on Bibsonomy LATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Chao Han, Adit D. Singh Testing cross wire opens within complex gates. Search on Bibsonomy VTS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Manuel J. Barragan, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter Special session: Hot topics: Statistical test methods. Search on Bibsonomy VTS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yu Wang, Adit D. Singh An Efficient Transition Detector Exploiting Charge Sharing. Search on Bibsonomy VLSI Design The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. Search on Bibsonomy VLSI Design The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ilia Polian, Jie Jiang, Adit D. Singh Detection conditions for errors in self-adaptive better-than-worst-case designs. Search on Bibsonomy ETS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Error detection and recovery in better-than-worst-case timing designs. Search on Bibsonomy ETS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jie Zou, Chao Han, Adit D. Singh Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. Search on Bibsonomy ATS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. Search on Bibsonomy ATS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Chao Han, Adit D. Singh Improving CMOS open defect coverage using hazard activated tests. Search on Bibsonomy VTS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Chao Han, Adit D. Singh On the testing of hazard activated open defects. Search on Bibsonomy ITC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Search on Bibsonomy VLSI Design The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. Search on Bibsonomy VLSI Design The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. Search on Bibsonomy VLSI-SoC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello Current testing: Dead or alive? Search on Bibsonomy ETS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Chao Han, Adit D. Singh Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. Search on Bibsonomy Asian Test Symposium The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia Special session 4B: Elevator talks. Search on Bibsonomy VTS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. Search on Bibsonomy VLSI Design The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendra Boolchandani, Virendra Singh, Adit D. Singh (eds.) VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers Search on Bibsonomy VDAT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita SEU tolerant robust memory cell design. Search on Bibsonomy IOLTS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Xi Qian, Chao Han, Adit D. Singh Detection of gate-oxide defects with timing tests at reduced power supply. Search on Bibsonomy VTS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita SEU Tolerant Robust Latch Design. Search on Bibsonomy VDAT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. Search on Bibsonomy Asian Test Symposium The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh SSTKR: Secure and Testable Scan Design through Test Key Randomization. Search on Bibsonomy Asian Test Symposium The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Xi Qian, Adit D. Singh, Abhijit Chatterjee Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. Search on Bibsonomy Asian Test Symposium The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Kautalya Mishra, Ahmed Faraz, Adit D. Singh Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. Search on Bibsonomy VLSI Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli Adapting to adaptive testing. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh Modified T-Flip-Flop based scan cell for RAS. Search on Bibsonomy European Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Xi Qian, Adit D. Singh Distinguishing Resistive Small Delay Defects from Random Parameter Variations. Search on Bibsonomy Asian Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Amit Mishra 0002, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh Modified Scan Flip-Flop for Low Power Testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh Test application time minimization for RAS using basis optimization of column decoder. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Adit D. Singh, Chao Han, Xi Qian An output compression scheme for handling X-states from over-clocked delay tests. Search on Bibsonomy VTS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh On Minimization of Test Application Time for RAS. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Random Access Scan (RAS), DFT, Scan Design
1Balapradeep Gadamsetti, Adit D. Singh Current Sensing Completion Detection for high speed and area efficient arithmetic. Search on Bibsonomy APCCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar 0002, Christos A. Papachristou Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. Search on Bibsonomy IOLTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Adit D. Singh A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. Search on Bibsonomy DFT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal Output Hazard-Free Transition Delay Fault Test Generation. Search on Bibsonomy VTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. Search on Bibsonomy ITC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Scan Delay Testing of Nanometer SoCs. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Gefu Xu, Adit D. Singh Scan cell design for launch-on-shift delay tests with slow scan enable. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Gefu Xu, Adit D. Singh Achieving high transition delay fault coverage with partial DTSFF scan chains. Search on Bibsonomy ITC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Gefu Xu, Adit D. Singh Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF IC reliability, reliability simulation, design for reliability, interconnect, electromigration, defect modeling
1Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh New JETTA Editors, 2006. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF fault tolerance, reliability, testing
1Gefu Xu, Adit D. Singh Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Adit D. Singh, Gefu Xu Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Hazard-Free, Test, Delay, Transition
1Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Pseudo Dual Supply Voltage Domino Logic Design. Search on Bibsonomy J. Low Power Electronics The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Low-power domino circuits using NMOS pull-up on off-critical paths. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh, Gefu Xu Delay Defect Characterization Using Low Voltage Test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Adit D. Singh T2: Statistical Methods for VLSI Test and Burn-in Optimization. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Gefu Xu, Adit D. Singh Low Voltage Test in Place of Fast Clock in DDSI Delay Test. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF delay test, defect, ATE, low voltage test
1Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Adit D. Singh A self-timed structural test methodology for timing anomalies due to defects and process variations. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh A random access scans architecture to reduce hardware overhead. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. Search on Bibsonomy European Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh Reduce Yield Loss in Delay Defect Detection in Slack Interval. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh Low-power dual Vth pseudo dual Vdd domino circuits. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
1Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh Sizing CMOS Circuits for Increased Transient Error Tolerance. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Thomas S. Barnett, Adit D. Singh, Victor P. Nelson Extending integrated-circuit yield-models to estimate early-life reliability. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan Multimode scan: Test per clock BIST for IP cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF SoC, BIST, scan, digital testing
1Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa IC Reliability Simulator ARET and Its Application in Design-for-Reliability. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Haihua Yan, Adit D. Singh Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Adit D. Singh Should Nanometer Circuits be Periodically Tested in the Field? Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Thomas S. Barnett, Adit D. Singh Relating Yield Models to Burn-In Fall-Out in Time. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Michael Gössel, Egor S. Sogomonyan, Adit D. Singh Scan-Path with Directly Duplicated and Inverted Duplicated Registers. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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