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Publications of "Anees Ullah" ( http://dblp.L3S.de/Authors/Anees_Ullah )

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Publication years (Num. hits)
2012-2019 (14)
Publication types (Num. hits)
article(9) inproceedings(5)
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Found 15 publication records. Showing 14 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Pedro Reviriego, Salvatore Pontarelli, Anees Ullah Error Detection and Correction in SRAM Emulated TCAMs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pedro Reviriego, Anees Ullah, Salvatore Pontarelli PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir, Giuseppe Bianchi 0001 Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays. Search on Bibsonomy HPSR The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nasim Ullah, Anees Ullah, Asier Ibeas, Jorge A. Herrera Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems. Search on Bibsonomy IEEE Access The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Matteo Sonza Reorda, Luca Sterpone, Anees Ullah An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Anees Ullah, Ernesto Sánchez 0001, Luca Sterpone, Luis Andres Cardona, Carles Ferrer 0001 An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Search on Bibsonomy Microelectronics Reliability The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer 0001 A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Anees Ullah, Luca Sterpone Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Ernesto Sánchez 0001, Luca Sterpone, Anees Ullah Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. Search on Bibsonomy FPL The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Matteo Sonza Reorda, Luca Sterpone, Anees Ullah An error-detection and self-repairing method for dynamically and partially reconfigurable systems. Search on Bibsonomy ETS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Luca Sterpone, Anees Ullah On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs. Search on Bibsonomy AHS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Luca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. Search on Bibsonomy AHS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Sadaqat ur Rehman, Muhammad Bilal, Basharat Ahmad, Khawaja Muhammad Yahya, Anees Ullah, Obaid ur Rehman Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN). Search on Bibsonomy CoRR The full citation details ... 2012 DBLP  BibTeX  RDF
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