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Publications of Antoni Roca 0001 Antoni Roca Perez ( http://dblp.L3S.de/Authors/Antoni_Roca_0001 )

  Author page on DBLP  Author page in RDF  Community of Antoni Roca 0001 in ASPL-2

Publication years (Num. hits)
2010-2013 (15) 2014-2017 (8)
Publication types (Num. hits)
article(9) inproceedings(14)
GrowBag graphs for keyword ? (Num. hits/coverage)

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Found 24 publication records. Showing 23 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Sergi Alcaide, Carles Hernández, Antoni Roca 0001, Jaume Abella DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. Search on Bibsonomy DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Lucas Machado, Antoni Roca Perez, Jordi Cortadella Voltage Noise Analysis with Ring Oscillator Clocks. Search on Bibsonomy ISVLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca 0001, Eduardo Quiñones, Francisco J. Cazorla Improving performance guarantees in wormhole mesh NoC designs. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca 0001, Sachin S. Sapatnekar Ring Oscillator Clocks and Margins. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, Mario Lodde, José Flich Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Search on Bibsonomy Computers & Electrical Engineering The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca 0001, Sachin S. Sapatnekar Reactive clocks with variability-tracking jitter. Search on Bibsonomy ICCD The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1José Cano, Jose Flich, Antoni Roca 0001, José Duato, Marcello Coppola, Riccardo Locatelli Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Javier de San Pedro, Jordi Cortadella, Antoni Roca 0001 A hierarchical approach for generating regular floorplans. Search on Bibsonomy ICCAD The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mario Lodde, Antoni Roca 0001, José Flich Built-in fast gather control network for efficient support of coherence protocols. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato Silicon-aware distributed switch architecture for on-chip networks. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, Federico Silla, Jose Flich, José Duato On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato Enabling High-Performance Crossbars through a Floorplan-Aware Design. Search on Bibsonomy ICPP The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Giorgos Dimitrakopoulos DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. Search on Bibsonomy FPL The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, José Flich, Federico Silla, José Duato Characterizing the impact of process variation on 45 nm NoC-based CMPs. Search on Bibsonomy J. Parallel Distrib. Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, Jose Flich, Federico Silla, José Duato Fault-Tolerant Vertical Link Design for Effective 3D Stacking. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Federico Silla, José Duato A low-latency modular switch for CMP systems. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, José Flich, Antoni Roca 0001, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato A Distributed Switch Architecture for On-Chip Networks. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF switch implementation, network-on-chip
1Jesús Camacho Villanueva, José Flich, Antoni Roca 0001, José Duato PC-Mesh: A Dynamic Parallel Concentrated Mesh. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, Federico Silla, Jose Flich, José Duato Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. Search on Bibsonomy NOCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, Jose Flich, Antoni Roca 0001, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. Search on Bibsonomy NOCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Fault-tolerance, Routing, Networks-on-chip
1Antoni Roca 0001, Jose Flich, Federico Silla, José Duato A Latency-Efficient Router Architecture for CMP Systems. Search on Bibsonomy DSD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Federico Silla, José Duato VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. Search on Bibsonomy HiPC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
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