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Publications of "ByongChan Lim" ( )

  Author page on DBLP  Author page in RDF  Community of ByongChan Lim in ASPL-2

Publication years (Num. hits)
2009-2019 (8)
Publication types (Num. hits)
article(3) inproceedings(5)
Venues (Conferences, Journals, ...)
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Found 9 publication records. Showing 8 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1ByongChan Lim, Mark Horowitz An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Steven Herbst, ByongChan Lim, Mark Horowitz Fast FPGA emulation of analog dynamics in digitally-driven systems. Search on Bibsonomy ICCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1ByongChan Lim, Mark Horowitz Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture. Search on Bibsonomy VLSI Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz Digital Analog Design: Enabling Mixed-Signal System Validation. Search on Bibsonomy IEEE Design & Test The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao Fortifying analog models with equivalence checking and coverage analysis. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
1ByongChan Lim, Jaeha Kim, Mark A. Horowitz An efficient test vector generation for checking analog/mixed-signal functional models. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits
1Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz Leveraging designer's intent: A path toward simpler analog CAD tools. Search on Bibsonomy CICC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
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