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article(972) book(7) incollection(14) inproceedings(3681) phdthesis(23) proceedings(7)
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Found 4704 publication records. Showing 4704 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
82Hyun-Gyu Kim, Hyeong-Cheol Oh A DSP-Enhanced 32-Bit Embedded Microprocessor. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD
80Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man Synthesis of pipelined DSP accelerators with dynamic scheduling. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
76Wei-Kai Cheng, Youn-Long Lin Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF code generation, DSP
76David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. Search on Bibsonomy FCCM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
76Catherine H. Gebotys, Robert J. Gebotys Designing for Low Power in Complex Embedded DSP Systems. Search on Bibsonomy HICSS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
74Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita Power analysis and low-power scheduling techniques for embedded DSP software. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
68Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW
68Jung L. Lee, Myung Hoon Sunwoo Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multimedia, DSP, instruction
68Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. Search on Bibsonomy RTCSA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
68Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. Search on Bibsonomy CASES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
68Catherine H. Gebotys, Robert J. Gebotys Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability. Search on Bibsonomy HICSS (3) The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
67Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee Enabling compiler flow for embedded VLIW DSP processors with distributed register files. Search on Bibsonomy LCTES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF distributed register files, embedded VLIW DSP compilers, software pipelining
67Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen A compact DSP core with static floating-point unit & its microcode generation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF DSP core, digital signal processor, floating-point units
66J. Geoffrey Chase, Christopher G. Pretty, Alex Bedarida, Philippe Bettler An Applications-Based Approach to Measuring DSP Efficiency. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Reconfigurable DSP, Signal Processing, DSP Architecture, Application Analysis
64Roger F. Woods, John V. McCanny, John G. McWhirter From Bit Level Systolic Arrays to HDTV Processor Chips. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SoC architectures, DSP systems, pipelining, systolic arrays
61Xi-min Wang, Zhe Wang Design and Implementation of Memory Pools for Embedded DSP. Search on Bibsonomy CSSE (2) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
61Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen A Compact DSP Core with Static Floating-Point Arithmetic. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
61Peter Koch 0001 A Project-oriented Master Programme in "DSP Algorithms and ASIC Architectures". Search on Bibsonomy MSE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
60Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Sied Mehdi Fakhraie MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications. Search on Bibsonomy MASCOTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF MDST, Multiprocessor DSP Simulation toolkit, Voice processing applications
58Fei Dai 0001, Jie Wu 0001 Efficient Broadcasting in Ad Hoc Wireless Networks Using Directional Antennas. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF self-pruning, simulation, broadcasting, directional antennas, Ad hoc wireless networks, localized algorithms
58Fei Dai 0001, Jie Wu 0001 Efficient Broadcasting in Ad Hoc Networks Using Directional Antennas. Search on Bibsonomy NETWORKING The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
58Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
57Uwe Meyer-Bäse, Antonio García, Fred J. Taylor Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
56Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF digital signal processing (DSP) systems, electromagnetic interference (EMI), speech recognition system (SRS), on-line testing, noise immunity
54Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF real-time, probability, DSP, DVS, assignment
54Saulo Oliveira Dornellas Luiz, Genildo de Moura Vasconcelos, Leandro Dias da Silva Formal specification of DSP gateway for data transmission between processor cores of OMAP platform. Search on Bibsonomy SAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF OMAP161x platform, modelling, model checking, embedded systems, timed-automata, discrete event systems, inter-processor communication
54Shiv Balakrishnan, Chris Eddington Efficient DSP algorithm development for FPGA and ASIC technologies. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara SoC with an integrated DSP and a 2.4-GHz RF transmitter. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
54Hyun-Gyu Kim, Hyeong-Cheol Oh A Low-Power DSP-Enhanced 32-Bit EISC Processor. Search on Bibsonomy HiPEAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
54Chia-Jui Hsu, Shuvra S. Bhattacharyya Porting DSP Applications across Design Tools Using the Dataflow Interchange Format. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
54Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee Compiler Optimizations with DSP-Specific Semantic Descriptions. Search on Bibsonomy LCPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
54Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley A Multi-Level Memory System Architecture for High-Performance DSP Applications. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
52Catherine H. Gebotys DSP address optimization using a minimum cost circulation technique. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF DSP software compliation, DSP addressing, Applied Optimization, Network Flow, software synthesis
51Partha Biswas, Nikil D. Dutt Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
51Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee Automatic translation of software binaries onto FPGAs. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF compiler, reconfigurable computing, binary translation, hardware-software co-design, decompilation
50Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas Architecture and Evaluation of an Asynchronous Array of Simple Processors. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
47Hani Rizk, Christos A. Papachristou, Francis G. Wolff A Self Test Program Design Technique for Embedded DSP Cores. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF self test programs, pseudorandom BIST, LSFR, DSP, ATPG
47Y. Wang, Y. Tang, Y. Jiang, Y.-G. Chung, S.-S. Song, M.-S. Lim Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors. Search on Bibsonomy IEEE Trans. Signal Processing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia JouleQuest: An Accurate Power Model for the StarCore DSP Platform. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Behzad Akbarpour, Sofiène Tahar An approach for the formal verification of DSP designs using Theorem proving. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files. Search on Bibsonomy LCPC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee Compiler Supports and Optimizations for PAC VLIW DSP Processors. Search on Bibsonomy LCPC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Catherine H. Gebotys, Robert J. Gebotys An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
47Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
46Dong-Ik Ko, Shuvra S. Bhattacharyya Modeling of Block-Based DSP Systems. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DSP software synthesis, quasi-static scheduling, memory management, dataflow modeling
46David P. Magee Matlab extensions for the development, testing and verification of real-time DSP software. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF C intrinsics, DSP software, optimization, verification, matlab
46Bernhard Rinner, Martin Schmid, Reinhold Weiss Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multi-DSP architectures, task reconfiguration, embedded system, rapid prototyping, testability
46Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum Briefing a New Approach to Improve the EMI Immunity of DSP Systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Digital Signal Processing (DSP) Systems, Electromagnetic Interference (EMI), On-Line Testing, Noise Immunity
46Christopher G. Pretty, J. Geoffrey Chase Reconfigurable DSP's for Efficient MPEG-4 Video and Audio Decoding. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Multimedia, Video, Signal Processing, Audio, MPEG-4, DSP Architecture, Application Analysis
43Byeong-Doo Choi, Min-Cheol Hwang, Ju-Hun Nam, Kyung-Hoon Lee, Sung-Jea Ko High-Performance Motion-JPEG2000 Encoder Using Overlapped Block Transferring and Pipelined Processing. Search on Bibsonomy PCM (2) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF OBT, Wavelet, DSP, JPEG2000
43Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43B. Bosi, Guy Bois, Yvon Savaria Reconfigurable pipelined 2-D convolvers for fast digital signal processing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
43Sati Banerjee, Paul M. Chau, Ronald D. Fellman Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
42Partha Biswas, Nikil D. Dutt Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
41Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
41Inki Hong, Miodrag Potkonjak, Ramesh Karri Power optimization using divide-and-conquer techniques for minimization of the number of operations. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF DSP computations, architectural techniques, divide-and-conquer compilation, portable wireless DSP applications, compilation, power consumption, data flow graphs
40Guoqiang Xu, Mei Xie License Plate Multi-DSP and Multi-FPGA Design and Realization in Highway Toll System. Search on Bibsonomy ISICA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA, DSP, License Plate Recognition
40Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance. Search on Bibsonomy Journal of Intelligent and Robotic Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint
40Messaoud Ahmed-Ouameur, Daniel Massicotte Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF delay acquisition, Wiener LMS, FPGA, VLSI, FFT, DSP, WCDMA, channel estimation, cdma2000
40Hai Yan, Shengli Zhou, Zhijie Jerry Shi, Baosheng Li A DSP implementation of OFDM acoustic modem. Search on Bibsonomy Underwater Networks The full citation details ... 2007 DBLP  DOI  BibTeX  RDF acoustic modem, DSP, OFDM, multicarrier
40Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF PD77210, successive similarity detection algorithm (SSDA), DMA queue, low power, motion estimation, DSP, MPEG-4, computational cost
40Brad L. Hutchings, Brent E. Nelson GigaOp DSP on FPGA. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, DSP
40Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys Automatic floating-point to fixed-point conversion for DSP code generation. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point
39Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
39Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya Memory-constrained Block Processing for DSP Software Optimization. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF block processing, block diagram compiler, activation overhead, embedded systems, memory management, vectorization, dataflow, context switch
39Hongfu Zhou DC Servo System Design Based on Fuzzy Control with DSP. Search on Bibsonomy ICNSC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Cameron H. G. Wright, Michael G. Morrow, Mark C. Allie, Thad B. Welch Enhancing engineering education and outreach using real-time DSP. Search on Bibsonomy ICASSP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF block diagram compiler, hierarchical graph decomposition, procedural implementation, embedded systems, design methodology, memory optimization, Synchronous dataflow
39Babak Zamanlooy, Vahid Hamiati Vaghef, Sattar Mirzakuchaki, Ali Shojaee Bakhtiari, Reza Ebrahimi Atani A Real Time Infrared Imaging System Based on DSP & FPGA. Search on Bibsonomy PSIVT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF IRFPA, Nonuniformity Detection, Nonuniformity Correction
39Chien-Chih Liu, Hsueh-Ming Hang Acceleration and Implementation of JPEG2000 Encoder on TI DSP Platform. Search on Bibsonomy ICIP (3) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang Real-Time DSP Implementation on Local Stereo Matching. Search on Bibsonomy ICME The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya Memory-constrained Block Processing Optimization for Synthesis of DSP Software. Search on Bibsonomy ICSAMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan Automatic synthesis and scheduling of multirate DSP algorithms. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Kiyotaka Takahashi, Eigo Mori Architectural Design of a DSP Scripting Language for Mobile Multimedia Terminals. Search on Bibsonomy AINA (2) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. Search on Bibsonomy SCOPES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Jae Sung Lee, Myung Hoon Sunwoo Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF application specific digital signal processor, DMT, fast Fourier transform, OFDM
39Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou Parameterized and low power DSP core for embedded systems. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Madhubanti Mukherjee, Ranga Vemuri A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Francesco Pessolano, Joep L. W. Kessels, Ad M. G. Peeters MDSP: A High-Performance Low-Power DSP Architecture. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao An embedded DSP core for wireless communication. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Jung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm. Search on Bibsonomy ISCAS (5) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair Performance Considerations in Embedded DSP based System-On-a-Chip Designs. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Mike J. G. Lewis, L. E. M. Brackenbury Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Anu Purhonen Quality Attribute Taxonomies for DSP Software Architecture Design. Search on Bibsonomy PFE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39S. Ramanathan, S. K. Nandy, V. Visvanathan Reconfigurable Filter Coprocessor Architecture for DSP Applications. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
39David W. Currie, Alan J. Hu, Sreeranga P. Rajan Automatic formal verification of DSP software. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Soohwan Ong, Hyunjune Yoo, Myung Hoon Sunwoo A MDSP (multimedia DSP) chip for portable multimedia applications. Search on Bibsonomy ISCAS (4) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Ingrid Verbauwhede, Mihran Touriguian A Low Power DSP Engine for Wireless Communications. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
39Hanho Lee, Gerald E. Sobelman Digit-Serial DSP Library for Optimized FPGA Configuration. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
39Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita Power analysis and minimization techniques for embedded DSP software. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man Synthesis of pipelined DSP accelerators with dynamic scheduling. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Catherine H. Gebotys An optimal methodology for synthesis of DSP multichip architectures. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
39Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala DSP design tool requirements for embedded systems: A telecommunications industrial perspective. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
39Daw-Tung Lin, Chung-Yu Yang H.264/AVC Video Encoder Realization and Acceleration on TI DM642 DSP. Search on Bibsonomy PSIVT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF H.264/AVC encoder, TM320DM642 DSP, optimization, motion estimation, quantization, mode decision
39Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF VLIW DSP processor, optimizing context switch overhead, microkernel design
39Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals. Search on Bibsonomy J. Electronic Testing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta
39Yu-Chun Peng, Meng-Ting Lu, Homer H. Chen DSP implementation of digital image stabilizer. Search on Bibsonomy ICME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF BF561 analog device, DSP implementation, digital image stabilization algorithm, hand-held video camera, block-based motion estimation, image sequence, digital signal processing, median filter
39Wei Zhao, Christos A. Papachristou Synthesis of reusable DSP cores based on multiple behaviors. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips
36Hong Yue, Zhiying Wang, Kui Dai A Heterogeneous Embedded MPSoC for Multimedia Applications. Search on Bibsonomy HPCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC
36Andrew A. Lamb, William Thies, Saman P. Amarasinghe Linear analysis and optimization of stream programs. Search on Bibsonomy PLDI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF algebraic simplification, optimization, embedded, FFT, DSP, linear systems, stream programming, StreamIt
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