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Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )

URL (DBLP): http://dblp.uni-trier.de/db/conf/eurodac

Publication years (Num. hits)
1990 (121) 1991 (101) 1992 (121) 1993 (91) 1994 (107) 1995 (94) 1996 (87)
Publication types (Num. hits)
inproceedings(715) proceedings(7)
Venues (Conferences, Journals, ...)
EURO-DAC(722)
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The graphs summarize 94 occurrences of 55 keywords

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Found 722 publication records. Showing 722 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ayman M. Wahba, Dominique Borrione Automatic diagnosis may replace simulation for correcting simple design errors. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Dirk Rabe, Wolfgang Nebel New approach in gate-level glitch modelling. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Konrad Feyerabend, Rainer Schlör Hardware synthesis from requirement specifications. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Bogdan G. Arsintescu, Sorin A. Spânoche Global stacking for analog circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Valentina Salapura, Volker Hamann Implementing fuzzy control systems using VHDL and statecharts. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Rhodri M. Davies, John V. Woods Timing verification for asynchronous design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Zeljko Mrcarica, Helmut Detter, D. Glozic, Vanco B. Litovski Describing space-continuous models of microelectromechanical devices for behavioral simulation. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antônio C. Mesquita, Aloysio Pedroza, Luci Pirmez Analysis of different protocol description styles in VHDL for high-level synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Eduardo de la Torre, J. Calvo, Javier Uceda Model generation of test logic for macrocell based designs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Gunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder A VHDL reuse workbench. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Sabih H. Gerez, Erwin G. Woutersen Assignment of storage values to sequential read-write memories. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Claus Schneider, Wolfgang Ecker Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich Incremental re-encoding for symbolic traversal of product machines. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Youn-Long Lin, Tsung-Yi Wu Storage optimization by replacing some flip-flops with latches. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Vladimir B. Dmitriev-Zdorov Generalized coupling as a way to improve the convergence in relaxation-based solvers. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Matthias A. Senn, Peter H. Schneider, Bernd Wurth Power analysis for sequential circuits at logic level. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Michael Gschwind, Dietmar Maurer An extendable MIPS-I processor kernel in VHDL for hardware/software co-design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Franz J. Rammig Beyond VHDL: textual formalisms, visual techniques, or both? Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Ulrich Bretthauer, Ernst-Helmut Horneber BRASIL: the Braunschweig mixed-mode-simulator for integrated circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Christoph Grimm 0001, Klaus Waldschmidt KIR - a graph-based model for description of mixed analog/digital systems. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara A hierarchical approach to analog behavioral modeling of neural networks using HDL-A. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Georg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer Hardware/software-cosimulation for mechatronic system design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Stefan Höreth Compilation of optimized OBDD-algorithms. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Vladimir A. Shepelev, Stephen W. Director Automatic workflow generation. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Markus Schwiegershausen, Holger Kropp, Peter Pirsch A system level HW/SW partitioning and optimization tool. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1T. Murayama, Yuji Gendai A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Francesco Curatelli, Marco Chirico, Leonardo Mangeruca Specification and management of timing constraints in behavioral VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Andreas Hett, Bernd Becker 0001, Rolf Drechsler MORE: an alternative implementation of BDD packages by multi-operand synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Kenneth Y. Yun Automatic synthesis of extended burst-mode circuits using generalized C-elements. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Ekambaram Balaji, Prabhu Krishnamurthy Modeling ASIC memories in VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Mitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki A practical clock router that accounts for the capacitance derived from parallel and cross segments. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Yankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser An approach for integrated specification and design of real-time systems. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Massoud Pedram, Jui-Ming Chang Module assignment for low power. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Stefano Quer, Gianpiero Cabodi, Paolo Camurati Decomposed symbolic forward traversals of large finite state machines. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Arno Kunzmann Efficient random testing with global weights. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Jürgen Bortolazzi, Thomas Hirth, Thomas Raith Specification and design of electronic control units. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Tobias H. Abthoff, Frank M. Johannes TINA: analog placement using enumerative techniques capable of optimizing both area and net length. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Enrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto BDD-based testability estimation of VHDL designs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Peter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín A refinement calculus for VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1D. Gareth Evans, Peter N. Green, Derrick Morris An integrated approach to engineering computer systems. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1C.-J. Richard Shi Entity overloading for mixed-signal abstraction in VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Wendell C. Baker, A. Richard Newton The maximal VHDL subset with a cycle-level abstraction. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar Testable path delay fault cover for sequential circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser A new concept for accurate modeling of VLSI interconnections and its application for timing simulation. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer 0002, Barry M. Pangrle, Rob Verbrugghe A system for compiling and debugging structured data processing controllers. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo Timing optimization by an improved redundancy addition and removal technique. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Graham Symonds, Wolfgang Nebel (eds.) Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996 Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  BibTeX  RDF
1Peter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Giovanni De Micheli, Vincnet J. Mooney III, Claudionor Nunes Coelho, Toshiyuki Sakamoto Synthesis from mixed specifications. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan Component selection in resource shared and pipelined DSP applications. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski Clock optimization for high-performance pipelined design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Rainer Leupers, Peter Marwedel Instruction selection for embedded DSPs with complex instructions. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Michael J. Knieser, Christos A. Papachristou COMET: a hardware-software codesign methodology. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Teresa Riesgo, Javier Uceda A fault model for VHDL descriptions at the register transfer level. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Michael Ryba, Utz G. Baitinger An integrated concept for design project planning and design flow control. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Mariagiovanna Sami, Anna Antola, Vincenzo Piuri A high-level synthesis approach to optimum design of self-checking circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Heinz-Josef Eikerling, Wolfgang Rosenstiel Automatic structuring and optimization of hierarchical designs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Guido Schumacher, Wolfgang Nebel Object-oriented hardware modelling - where to apply and what are the objects? Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Stephanus Büttgenbach Spotlights on recent developments in microsystem technology. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Christian Veith, Klaus Buchenrieder, Andreas Pyttel Mapping statechart models onto an FPGA-based ASIP architecture. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Krzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski Synchronous parallel controller synthesis from behavioural multiple-process VHDL description. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Sanjiv Narayan, Daniel D. Gajski Rapid performance estimation for system design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Karl van Rompaey, Ivo Bolsens, Hugo De Man, Diederik Verkest CoWare - a design environment for heterogenous hardware/software systems. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Adel Changuel, Ahmed Amine Jerraya, Robin Rolland Design of an adaptive motors controller based on fuzzy logic using behavioral synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1J. Bullmann, Wolfgang Rosenstiel, E. Schubert, Udo Kebschull Library based technology mapping using multiple domain representations. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Wolfgang Süß, Horst Eggert, Martina Gorges-Schleuter, Wilfried Jakob, S. Meinzer, Alexander Quinte Simulation and design optimization of microsystems based on standard simulators and adaptive search techniques. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Takashi Mitsuhashi, Masami Murakata, Kenji Yoshida, T. Aoki Physical design CAD in deep sub-micron era. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Andrew Crews, Forrest Brewer Controller optimization for protocol intensive applications. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Klaus D. Müller-Glaser CAD of microsystems - a challenge for system engineering. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Ivan Hom, John J. Granacki Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Manfred Koegst, Klaus Feske, Günter Franke State assignment for FSM low power design. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Ambar Sarkar System design using an integrated specification and performance modeling methodology. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Kevin O'Brien, Serge Maginot, Anne Robert Towards maximising the use of structural VHDL for synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Mohamed Abid, Adel Changuel, Ahmed Amine Jerraya Exploration of hardware/software design space through a codesign of robot arm controller. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Ernst Christen, Kenneth Bakalar VHDL 1076.1 - analog and mixed signal extensions to VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Armin Bender MILP based task mapping for heterogeneous multiprocessor systems. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Christos A. Papachristou, Mehrdad Nourani False path exclusion in delay analysis of RTL-based datapath-controller designs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Claus Mayer, Jörg Pleickhardt, Hans Sahm A graphical data management system for HDL-based ASIC design projects. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Vinoo Srinivasan, Nand Kumar, Ranga Vemuri Hierarchical behavioral partitioning for multicomponent synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli Hardware/software partitioning of VHDL system specifications. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Henrik Esbensen, Ernest S. Kuh EXPLORER: an interactive floorplanner for design space exploration. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Donatella Sciuto, Luciano Baresi, Cristiana Bolchini Software methodologies for VHDL code static analysis based on flow graphs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1M. Robson, G. Russell A digital method for testing embedded switched capacitor filters. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda Fault tolerant and BIST design of a FIFO cell. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1João Paulo Teixeira, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos VHDL fault simulation for defect-oriented test and diagnosis of digital ICs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Theodore Karoubalis, George Alexiou, Nick Kanopoulos Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs). Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Serafín Olcoz, Luis Entrena, Luis Berrojo An effective system development environment based on VHDL prototyping. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1D. Galán, Carlos J. Jiménez, Angel Barriga Barros, Santiago Sánchez-Solano VHDL package for description of fuzzy logic controllers. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Eugen Röhm Latest benchmark results of VHDL simulation systems. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Enrico Macii, Massimo Poncino Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Smita Bakshi, Daniel D. Gajski A memory selection algorithm for high-performance pipelines. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Franco Fummi, U. Rovati, Donatella Sciuto Testable synthesis of high complex control devices. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Laurent Arditi, Hélène Collavizza Towards verifying VHDL descriptions of processors. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Zahir Moosa, Nick Filer, Michael Brown, J. Heaton, J. Pye Practical inter-operation of CAD tools using a flexible procedural interface. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins Performance-oriented placement and routing for field-programmable gate arrays. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Mahsa Vahidi, Alex Orailoglu Metric-based transformations for self testable VLSI designs with high test concurrency. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Ulrike Ober, Manfred Glesner Multiway netlist partitioning onto FPGA-based board architecture. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Ulrich Weinmann, Oliver Bringmann 0001, Wolfgang Rosenstiel Device selection for system partitioning. Search on Bibsonomy EURO-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
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