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Publications at "FMCAD"( http://dblp.L3S.de/Venues/FMCAD )

URL (DBLP): http://dblp.uni-trier.de/db/conf/fmcad

Publication years (Num. hits)
1996 (33) 1998 (35) 2000 (33) 2002 (24) 2004 (31) 2006 (27) 2007 (32) 2008 (30) 2009 (31) 2010 (40) 2011 (35) 2012 (32) 2013 (38) 2014 (36) 2015 (30) 2016 (35) 2017 (37) 2018 (30)
Publication types (Num. hits)
inproceedings(571) proceedings(18)
Venues (Conferences, Journals, ...)
FMCAD(589)
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The graphs summarize 19 occurrences of 19 keywords

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Found 589 publication records. Showing 589 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1John Backes, Pauline Bolignano, Byron Cook, Catherine Dodge, Andrew Gacek, Kasper Luckow, Neha Rungta, Oksana Tkachuk, Carsten Varming Semantic-based Automated Reasoning for AWS Access Policies using SMT. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sourav Anand, Nadia Polikarpova Automatic Synchronization for GPU Kernels. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Heiko Becker, Nikita Zyuzin, Raphaël Monat, Eva Darulova, Magnus O. Myreen, Anthony C. J. Fox A Verified Certificate Checker for Finite-Precision Error Bounds in Coq and HOL4. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Grigory Fedyukovich, Sumanth Prabhu, Kumar Madhukar, Aarti Gupta Solving Constrained Horn Clauses Using Syntax and Data. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nina Narodytska Formal Verification of Deep Neural Networks. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Pavel Cadek, Clemens Danninger, Moritz Sinn, Florian Zuleger Using Loop Bound Analysis For Invariant Generation. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Thomas Pani, Georg Weissenbacher, Florian Zuleger Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Roberto Cavada, Alessandro Cimatti, Sergio Mover, Mirko Sessa, Giuseppe Cadavero, Giuseppe Scaglione Analysis of Relay Interlocking Systems via SMT-based Model Checking of Switched Multi-Domain Kirchhoff Networks. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hossein Hojjat, Philipp Rümmer The ELDARICA Horn Solver. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Peter Backeman, Philipp Rümmer, Aleksandar Zeljic Bit-Vector Interpolation and Quantifier Elimination by Lazy Reduction. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dejan Jovanovic, Andrew Reynolds The FMCAD 2018 Graduate Student Forum. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bernhard K. Aichernig, Roderick Bloem, Masoud Ebrahimi, Martin Tappler, Johannes Winter Automata Learning for Symbolic Execution. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alberto Griggio, Marco Roveri, Stefano Tonetta Certifying Proofs for LTL Model Checking. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Daniel Neider, Ivan Gavran Learning Linear Temporal Properties. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bjørnar Luteberget, Koen Claessen, Christian Johansen Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Cristian Mattarei, Makai Mann, Clark Barrett, Ross G. Daly, Dillon Huff, Pat Hanrahan CoSA: Integrated Verification for Agile Hardware Design. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nikolaj Bjørner, Arie Gurfinkel (eds.) 2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018 Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  BibTeX  RDF
1Alexander Ivrii, Ziv Nevo, Jason Baumgartner k-FAIR = k-LIVENESS + FAIR Revisiting SAT-based Liveness Algorithms. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vikas Rao, Utkarsh Gupta, Irina Ilioaea, Arpitha Srinath, Priyank Kalla, Florian Enescu Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Oded Padon, Jochen Hoenicke, Kenneth L. McMillan, Andreas Podelski, Mooly Sagiv, Sharon Shoham Temporal Prophecy for Proving Temporal Properties of Infinite-State Systems. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Roderick Bloem, Nicolas Braud-Santoni, Vedad Hadzic, Uwe Egly, Florian Lonsing, Martina Seidl Expansion-Based QBF Solving Without Recursion. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hernán Ponce de León, Florian Furbach, Keijo Heljanko, Roland Meyer BMC with Memory Models as Modules. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Julien Brunel, David Chemouil, Jeanne Tawa Analyzing the Fundamental Liveness Property of the Chord Protocol. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Parosh Aziz Abdulla, Mohamed Faouzi Atig, Yu-Fang Chen, Bui Phi Diep, Lukás Holík, Ahmed Rezine, Philipp Rümmer Trau: SMT solver for string constraints. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Adrian Rebola-Pardo, Luís Cruz-Filipe Complete and Efficient DRAT Proof Checking. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Supratik Chakraborty, Dror Fried, Lucas M. Tabajara, Moshe Y. Vardi Functional Synthesis via Input-Output Separation. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Eugene Goldberg Complete Test Sets And Their Approximations. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Viktor Malík, Martin Hruska, Peter Schrammel, Tomás Vojnar Template-Based Verification of Heap-Manipulating Programs. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Oded Padon Deductive Verification of Distributed Protocols in First-Order Logic. Search on Bibsonomy FMCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tamás Tóth, Ákos Hajdu, András Vörös 0001, Zoltán Micskei, István Majzik Theta: A framework for abstraction refinement-based model checking. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Matteo Marescotti, Arie Gurfinkel, Antti Eero Johannes Hyvärinen, Natasha Sharygina Designing parallel PDR. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Arnaud Sangnier, Nathalie Sznajder, Maria Potop-Butucaru, Sébastien Tixeuil Parameterized verification of algorithms for oblivious robots on a ring. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Elaheh Ghassabani, Michael W. Whalen, Andrew Gacek Efficient generation of all minimal inductive validity cores. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Armin Biere, Tom van Dijk, Keijo Heljanko Hardware model checking competition 2017. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Christopher J. Banks, Marco Elver, Ruth Hoffmann, Susmit Sarkar, Paul Jackson, Vijay Nagarajan Verification of a lazy cache coherence protocol against a weak memory model. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Murphy Berzish, Vijay Ganesh, Yunhui Zheng Z3str3: A string solver with theory-aware heuristics. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Freek Verbeek, Nike van Vugt Estimating worst-case latency of on-chip interconnects with formal simulation. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yu-Fang Chen, Chih-Duo Hong, Anthony W. Lin, Philipp Rümmer Learning to prove safety over parameterised concurrent systems. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zeinab Ganjei, Ahmed Rezine, Petru Eles, Zebo Peng Safety verification of phaser programs. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton Property directed reachability with word-level abstraction. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Matthew S. Bauer, Umang Mathur, Rohit Chadha, A. Prasad Sistla, Mahesh Viswanathan 0001 Exact quantitative probabilistic model checking through rational search. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz goSAT: Floating-point satisfiability as global optimization. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shin'ichiro Matsuo How formal analysis and verification add security to blockchain-based systems. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daniela Ritirc, Armin Biere, Manuel Kauers Column-wise verification of multipliers using computer algebra. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yakir Vizel, Alexander Nadel, Sharad Malik Solving linear arithmetic with SAT-based model checking. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Rashmi Mudduluru, Pantazis Deligiannis, Ankush Desai, Akash Lal, Shaz Qadeer Lasso detection using partial-state caching. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Keijo Heljanko The FMCAD 2017 graduate student forum. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Anastasiia Izycheva, Eva Darulova On sound relative error bounds for floating-point arithmetic. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Leonardo Alt, Antti Eero Johannes Hyvärinen, Sepideh Asadi, Natasha Sharygina Duality-based interpolation for quantifier-free equalities and uninterpreted functions. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1William T. Hallahan, Ennan Zhai, Ruzica Piskac Automated repair by example for firewalls. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris Learning support sets in IC3 and Quip: The good, the bad, and the ugly. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Kyungmin Bae, Sicun Gao Modular SMT-based analysis of nonlinear hybrid systems. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sylvain Conchon, Amit Goel, Sava Krstic, Rupak Majumdar, Mattias Roux FAR-Cubicle - A new reachability algorithm for Cubicle. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Rohit Dureja, Kristin Yvonne Rozier FuseIC3: An algorithm for checking large design spaces. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Grigory Fedyukovich, Samuel J. Kaufman, Rastislav Bodík Sampling invariants from frequency distributions. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Klaus Havelund, Doron Peled, Dogan Ulus First order temporal logic monitoring with BDDs. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Cas Cremers Symbolic security analysis using the Tamarin prover. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Tom van Dijk, Robert Wille, Robert Meolic Tagged BDDs: Combining reduction rules from different decision diagram types. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Byron Cook Automated formal reasoning about AWS systems. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Arie Gurfinkel, Alexander Ivrii K-induction without unrolling. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Alessandro Cimatti, Sergio Mover, Mirko Sessa SMT-based analysis of switching multi-domain linear Kirchhoff networks. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hans-Peter Deifel, Merlin Göttlinger, Stefan Milius, Lutz Schröder, Christian Dietrich 0001, Daniel Lohmann Automatic verification of application-tailored OSEK kernels. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daryl Stewart, Georg Weissenbacher (eds.) 2017 Formal Methods in Computer Aided Design, FMCAD 2017, Vienna, Austria, October 2-6, 2017 Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  BibTeX  RDF
1Jade Alglave Coalition, intrigue, ambush, destruction and pride: Herding cats can be challenging. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Lucas M. Tabajara, Moshe Y. Vardi Factored boolean functional synthesis. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Wilfried Steiner Formal methods in industrial dependable systems design - The TTTech example. Search on Bibsonomy FMCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Christos H. Papadimitriou Understanding evolution through algorithms. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ermenegildo Tomasco, Truc L. Nguyen, Omar Inverso, Bernd Fischer 0002, Salvatore La Torre, Gennaro Parlato Lazy sequentialization for TSO and PSO via shared memory abstractions. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Dawn Song Formal verification for computer security: Lessons learned and future directions. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1George Varghese Network verification - When Clarke meets Cerf. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Dan R. Ghica, Achim Jung Categorical semantics of digital circuits. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler Equivalence checking using Gröbner bases. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jaideep Ramachandran, Thomas Wahl Integrating proxy theories and numeric model lifting for floating-point arithmetic. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bernd Finkbeiner, Markus N. Rabe Verifying hyperproperties of hardware systems. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Brian Campbell 0001, Ian Stark Extracting behaviour from an executable instruction set model. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hossein Hojjat The FMCAD 2016 graduate student forum. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Pavel Parizek Hybrid partial order reduction with under-approximate dynamic points-to and determinacy information. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Matthew Naylor, Simon W. Moore, Alan Mujumdar A consistency checker for memory subsystem traces. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Dejan Jovanovic, Bruno Dutertre Property-directed k-induction. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Pranav Ashar A paradigm shift in verification methodology. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hossein Hojjat, Philipp Rümmer, Jedidiah McClurg, Pavol Cerný, Nate Foster Optimizing horn solvers for network repair. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer, Bernd Becker 0001 Accurate ICP-based floating-point reasoning. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Alexander Nadel Routing under constraints. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin Verifiable hierarchical protocols with network invariants on parametric systems. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Susmit Jha, Vasumathi Raman, Sanjit A. Seshia On ∃ ∀ ∃! solving: A case study on automated synthesis of magic card tricks. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ruzica Piskac, Muralidhar Talupur (eds.) 2016 Formal Methods in Computer-Aided Design, FMCAD 2016, Mountain View, CA, USA, October 3-6, 2016 Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  BibTeX  RDF
1Eugene Goldberg Equivalence checking by logic relaxation. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Alastair Reid Trustworthy specifications of ARM® v8-A and v8-M system level architecture. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Rohit Singh 0002, Armando Solar-Lezama SWAPPER: A framework for automatic generation of formula simplifiers based on conditional rewrite rules. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ofer Guthmann, Ofer Strichman, Anna Trostanetski Minimal unsatisfiable core extraction for SMT. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Kenneth L. McMillan Modular specification and verification of a cache-coherent interface. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Guillaume Baudart, Timothy Bourke, Marc Pouzet Soundness of the quasi-synchronous abstraction. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Alain Mebsout, Cesare Tinelli Proof certificates for SMT-based model checkers for infinite-state systems. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1David L. Rager, Jo C. Ebergen, Dmitry Nadezhin, Austin Lee, Cuong Kim Chau, Ben Selfridge Formal verification of division and square root implementations, an Oracle report. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Tomoya Yamaguchi, Tomoyuki Kaga, Alexandre Donzé, Sanjit A. Seshia Combining requirement mining, software model checking and simulation-based verification for industrial automotive systems. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Roderick Bloem, Robert Könighofer, Ingo Pill, Franz Röck Synthesizing adaptive test strategies from temporal logic specifications. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Pavol Cerný Program synthesis for networks. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Manish Pandey Machine learning and systems for the next frontier in formal verification. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
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