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Publication years (Num. hits)
1988-1992 (20) 1993 (21) 1994 (75) 1995 (112) 1996 (112) 1997 (123) 1998 (220) 1999 (263) 2000 (289) 2001 (286) 2002 (353) 2003 (546) 2004 (698) 2005 (745) 2006 (1024) 2007 (977) 2008 (1045) 2009 (834) 2010 (701) 2011 (730) 2012 (702) 2013 (818) 2014 (808) 2015 (800) 2016 (853) 2017 (936) 2018 (859) 2019 (242)
Publication types (Num. hits)
article(3337) book(8) incollection(46) inproceedings(11668) phdthesis(107) proceedings(26)
Venues (Conferences, Journals, ...)
FPGA(1348) FPL(1268) FCCM(580) FPT(366) ReConFig(332) ISCAS(299) CoRR(229) IEEE Trans. VLSI Syst.(207) DATE(204) DSD(204) ARC(196) IPDPS(193) DAC(160) IEEE Trans. on CAD of Integrat...(141) Microprocessors and Microsyste...(136) ASAP(123) More (+10 of total 1583)
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Found 15192 publication records. Showing 15192 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
97Vaughn Betz, Jonathan Rose Automatic generation of FPGA routing architectures from high-level descriptions. Search on Bibsonomy FPGA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
89Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
81Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF loongson, multi-fpga, fpga, evaluation, verification, emulation
77Husain Parvez, Zied Marrakchi, Habib Mehrez Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asif, fpga, architecture, application specific, cad
72Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong Performance benefits of monolithically stacked 3D-FPGA. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3D monolithically stacked, FPGA, performance analysis
72Ian Kuon, Aaron Egier, Jonathan Rose Design, layout and verification of an FPGA using automated tools. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA, programmable logic, PLD, automatic layout
69Nicholas Weaver, John R. Hauser, John Wawrzynek The SFRA: a corner-turn FPGA architecture. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
68Nathaniel Couture, Kenneth B. Kent Periodic licensing of FPGA based intellectual property. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
66Yohei Matsumoto, Hanpei Koike, Akira Masaki FPGAs with multidimensional mesh topology. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
65Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj 3D configuration caching for 2D FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
63Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001 FPGA prototyping of an amba-based windows-compatible SoC. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, microsoft windows, amba, x86
60Jianzhong Shi, Akash Randhar, Dinesh Bhatia Macro Block Based FPGA Floorplanning. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
60Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong Architecture evaluation for power-efficient FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGA power model, low power design, FPGA architecture
58Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 Intel nehalem processor core made FPGA synthesizable. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF intel nehalem, synthesizable core, fpga, emulator
58Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dynamic inspection, reconfigurable microprocessors, fpga
58Yangyang Pan, Tong Zhang 0002 DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dram-based fpga, memory stacking, 3d integration
58Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 Intel® atomTM processor core made FPGA-synthesizable. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF intel atom, synthesizable core, fpga, emulator
58Wei Mark Fang, Jonathan Rose Modeling routing demand for early-stage FPGA architecture development. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF model, FPGA, routing, architecture
58Mingjie Lin, Abbas El Gamal A routing fabric for monolithically stacked 3D-FPGA. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 3D monolithically stacked, FPGA, performance analysis, routing architecture
58Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy Power-aware RAM mapping for FPGA embedded memory blocks. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF embedded memory block, FPGA, dynamic power
58Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, low power, power efficient, dual-Vdd, dual-Vt
57Alastair M. Smith, Steven J. E. Wilton, Joydip Das Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga modeling, wirelength estimation, fpga, architecture design
57Yan Lin 0001, Fei Li 0003, Lei He 0001 Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
56Jason Cong, Kirill Minkovich Optimality study of logic synthesis for LUT-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
56Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers A quantitative analysis of the speedup factors of FPGAs over processors. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF performance, FPGA, analysis, VHDL, reconfigurable computing
54Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF ams testing, concurrent test development, behavioral modeling
54Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis A novel methodology for designing high-performance and low-energy FPGA routing architecture. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain Techniques for FPGA Implementation of Video Compression Systems. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
53Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta High-performance, energy-efficient platforms using in-socket FPGA accelerators. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF in-socket accelerator, fpga, agility
53Roto Le, Sherief Reda, R. Iris Bahar High-performance, cost-effective heterogeneous 3D FPGA architectures. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga, heterogeneous, 3d ic, switch box, through silicon via
53Server Kasap, Khaled Benkrid, Ying Liu A high performance fpga-based implementation of position specific iterated blast. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF psi-blast, fpga, blast, handel c
53Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
53Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne A novel FPGA logic block for improved arithmetic performance. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
53Amin Ansari, Keyvan Amiri Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF deinterleaver, pulse train, FPGA, parallel architecture
53Haoyu Song, John W. Lockwood Efficient packet classification for network intrusion detection using FPGA. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF BV, tree bitmap, FPGA, reconfigurable hardware, packet classification, TCAM, NIDS
53Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF basic cell, FPGA, CML, SiGe
53Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose Automatic transistor and physical design of FPGA tiles from an architectural specification. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGA, programmable logic, PLD, automatic layout
52Lerong Cheng, Yan Lin 0001, Lei He 0001 Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA power model, FPGA architecture
52Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen High-level languages: the future or a passing fad? Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF high-level design languages, RTL design
52Nathan Woods Integrating FPGAs in high-performance computing: the architecture and implementation perspective. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
52Deepak Rautela, Rajendra S. Katti Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer Soft multiprocessor systems for network applications (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Russell Tessier Incremental Compilation for Logic Emulation. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF virtual wire, scheduling, partitioning, incremental, logic emulation
51Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang Computation reuse in domain-specific optimization of signal recognition. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF computation reuse, signal recognition, fpga
51Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF simulator, FPGA, prototype, multiprocessor, multicore, emulator
51Tong Liu, Wei-Kang Huang, Fabrizio Lombardi Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF constant testability, FPGA, testing, manufacturing
51Walid A. Najjar Compiling code accelerators for FPGAs. Search on Bibsonomy CASES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA code acceleration
50Piyush Kumar Shukla, Sanjay Silakari, Sarita S. Bhadoria, Anuj Garg Multi-User FPGA - An Efficient Way of Managing Expensive FPGA Resources Using TCP/IP, Wi-Max/ Wi-Fi in a Secure Network Environment. Search on Bibsonomy ITNG The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Wi-Fi/ Wi-Max, NLOS, FPGA, AES, DES, Camellia, TDM
50Yee Jern Chong, Sri Parameswaran Flexible multi-mode embedded floating-point unit for field programmable gate arrays. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
50Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko Yield enhancements of design-specific FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
49Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
49Joshua Noseworthy, Miriam Leeser Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald The gigahertz FPGA: design consideration and applications. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006 Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Ivo Bolsens Challenges and Opportunities for FPGA Platforms. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Massoud Pedram, Bahman S. Nobandegani, Bryan Preas Design and analysis of segmented routing channels for row-based FPGA's. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
48Yi Shan, Bo Wang, Jing Yan, Yu Wang 0002, Ning-Yi Xu, Huazhong Yang FPMR: MapReduce framework on FPGA. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF FPGA framework, RankBoost, MapReduce
48Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu 32-bit floating-point FPGA gaussian elimination. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga., floating-point, gaussian elimination
48Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox FPGA technology mapping with encoded libraries andstaged priority cuts. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF priority cuts, fpga, synthesis, technology mapping
48Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt FPGA-based front-end electronics for positron emission tomography. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga, localization, timing, positron emission tomography
48Mingjie Lin The amorphous FPGA architecture. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF amorphous, FPGA, architecture, performance analysis
48Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun A practical FPGA-based framework for novel CMP research. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA-based emulation, transactional memory, chip multi-processor
48Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev 64-bit floating-point FPGA matrix multiplication. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA, matrix multiplication, floating-point
48Tom Kean Cryptographic rights management of FPGA intellectual property cores. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, cryptography, intellectual property, rights management
48J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF data-path optimization, floating-point/fixed-point conversion, hardware division, hyardware optimization, FPGA, floating-point, video-processing
47Sunwoo Kim, Won Woo Ro FPGA implementation of highly parallelized decoder logic for network coding (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, network coding, fpga implementation, galois field arithmetic
47Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA accelerators, c-to-gates, FPGA, high-performance computing, reconfigurable computing
47Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek Post-placement C-slow retiming for the xilinx virtex FPGA. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF C-slow retiming, FPGA CAD, FPGA optimization, retiming
47Janette Frigo, Maya Gokhale, Dominique Lavenier Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler
47Abdel Ejnioui, N. Ranganathan Routing on Switch Matrix Multi-FPGA Systems. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure
46Abderrahim Doumar, Hideo Ito Testing approach within FPGA-based fault tolerant systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
46Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu Towards scalable placement for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, convex optimization, quadratic placement, bipartite matching
46Chen Dong, Scott Chilstedt, Deming Chen FPCNA: a field programmable carbon nanotube array. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
46Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF adc, sd card, fpga, real-time, multiplexing, data acquisition, fft
46Robin Pottathuparambil, Ron Sass A parallel/vectorized double-precision exponential core to accelerate computational science applications. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF exponential core, fpga, cordic
46Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig Performance and power of cache-based reconfigurable computing. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches
46Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran When FPGAs are better at floating-point than microprocessors. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, floating-point, arithmetic
46Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF field programmable counter array (FPCA), FPGA
46Andy Gean Ye, Jonathan Rose Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
46Randy Huang, John Wawrzynek, André DeHon Stochastic, spatial routing for hypergraphs, trees, and meshes. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF spatial routing, FPGA, reconfigurable computing, detail routing
46Reza M. Rad, Mohammad Tehranipoor Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing. Search on Bibsonomy JETC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance, FPGA, reliability, CMOS, Nanotechnology
45Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
45Bryan Catanzaro, Brent E. Nelson Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45K. K. Lee, D. F. Wong Incremental reconfiguration of multi-FPGA systems. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Andy Yan, Rebecca Cheng, Steven J. E. Wilton On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Andreas Dandalis, Viktor K. Prasanna Configuration compression for FPGA-based embedded systems. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor Constraints from Hell: How to Tell Makes a Good FPGA (Panel). Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
45Steven Trimberger Scheduling Designs into a Time-Multiplexed FPGA. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
45Scott Hauck, Gaetano Borriello Logic Partition Orderings for Multi-FPGA Systems. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
45Vaughn Betz, Jonathan Rose Using Architectural "Families" to Increase FPGA Speed and Density. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
45Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong Performance Benefits of Monolithically Stacked 3-D FPGA. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Bryan Catanzaro, Brent E. Nelson Higher Radix Floating-Point Representations for FPGA-Based Arithmetic. Search on Bibsonomy FCCM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Andrzej Krasniewski Application-Dependent Testing of FPGA Delay Faults. Search on Bibsonomy EUROMICRO The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
44Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu 0006, Kirill Minkovich, Bo Yuan, Yi Zou Accelerating Monte Carlo based SSTA using FPGA. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF FPGA, monte carlo, SSTA
44Jason Cong, Kirill Minkovich LUT-based FPGA technology mapping for reliability (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
44Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
44Marcus Dutton, David C. Keezer An architecture for graphics processing in an FPGA (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, scalability, architecture, flexibility, gpu
44Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, routing algorithm, on-chip interconnect, router architecture
44Jonathan M. Johnson, Michael J. Wirthlin Voter insertion algorithms for FPGA designs using triple modular redundancy. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
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