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Publications at "HLDVT"( http://dblp.L3S.de/Venues/HLDVT )

URL (DBLP): http://dblp.uni-trier.de/db/conf/hldvt

Publication years (Num. hits)
2000 (29) 2001 (29) 2002 (33) 2003 (28) 2004 (32) 2005 (31) 2006 (33) 2007 (28) 2008 (26) 2009 (29) 2010 (26) 2011 (24) 2012 (25) 2016 (28) 2017 (16)
Publication types (Num. hits)
inproceedings(402) proceedings(15)
Venues (Conferences, Journals, ...)
HLDVT(417)
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Found 417 publication records. Showing 417 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Dömer Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Binod Kumar 0001, Kanad Basu, Masahiro Fujita, Virendra Singh RTL level trace signal selection and coverage estimation during post-silicon validation. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zahra Shirmohammadi, Hadi Zamani Sabzi, Seyed Ghassem Miremadi 3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Guy Barash, Eitan Farchi A randomized algorithm for constructing cross-feature tests from single feature tests. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sophia Balkovski, Ian G. Harris Designing cyber-physical systems from natural language descriptions. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Siroos Madani, Kasem Khalil, Bappaditya Dey, Devante Bonton, Magdy Bayoumi Repair techniques for aged TSVs in 3D integrated circuits. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1 2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017, Santa Cruz, CA, USA, October 5-6, 2017 Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  BibTeX  RDF
1Michele Lora Validation of HMI applications for industrial smart display. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Tonmoy Roy, Michael Hsiao Reachability analysis in RTL circuits using k-induction bounded model checking. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi A novel SAT-based ATPG approach for transition delay faults. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Keerthikumara Devarajegowda, Wolfgang Ecker On generation of properties from specification. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daniela De Venuto, Giovanni Mezzina, V. L. Gallo Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gait. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Pankaj Moharikar, Jayakrishna Guddeti Automated test generation for post silicon microcontroller validation. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Maral Amir, Tony Givargis HES machine: Harmonic equivalent state machine modeling for cyber-physical systems. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Masahiro Fujita An approach to approximate computing: Logic transformations for one-minterm changes in specification. Search on Bibsonomy HLDVT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Prab Varma, Miroslav N. Velev Welcome Message. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Qinhao Wang, Yusuke Kimura, Masahiro Fujita Automatically adjusting system level designs after RTL/gate-level ECO. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yusuke Kimura, Masahiro Fujita Specification by existing design plus use-cases. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Guantao Liu, Tim Schmidt, Rainer Dömer A segment-aware multi-core scheduler for system C PDES. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Natasa Miskov-Zivanov, Paolo Zuliani, Qinsi Wang, Edmund M. Clarke, James R. Faeder High-level modeling and verification of cellular signaling. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Md. Ariful Islam, Qinsi Wang, Ramin M. Hasani, Ondrej Balun, Edmund M. Clarke, Radu Grosu, Scott A. Smolka Probabilistic reachability analysis of the tap withdrawal circuit in caenorhabditis elegans. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Houssam Abbas, Zhihao Jiang, Kuk Jin Jang, Marco Beccani, Jackson Liang, Rahul Mangharam High-level modeling for computer-aided clinical trials of medical devices. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sebastian Reiter 0003, Alexander Viehl, Oliver Bringmann 0001, Wolfgang Rosenstiel Fault injection ecosystem for assisted safety validation of automotive systems. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jacob A. Abraham Cross-layer resilience: are high-level techniques always better? Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory Clock domain crossing formal verification: a meta-model. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Rosario Distefano, Nickolas Goncharenko, Franco Fummi, Rosalba Giugno, Gary D. Badery, Nicola Bombieri SyQUAL: a platform for qualitative modelling and simulation of biological systems. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mohamed O. Kayed, Mohamed Abdelsalam, Rafik Guindi Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Kasper Søe Luckow, Corina S. Pasareanu Log2model: inferring behavioral models from log data. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Daniel Yunge, Sangyoung Park, Philipp Kindt, Graziano Pravadelli, Samarjit Chakraborty Dynamic service synthesis and switching for medical IoT and ambient assisted living. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xian Li, Klaus Schneider 0001 Control-flow guided clause generation for property directed reachability. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jason G. Tong, Marc Boule, Zeljko Zilic Accelerating assertion assessment using GPUs. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Prachi Joshi, Vedahari Narasimhan G., Haibo Zeng, Sandeep K. Shukla, Chung-Wei Lin, Huafeng Yu Design space exploration for deterministic ethernet-based architecture of automotive systems. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Qinsi Wang, Edmund M. Clarke Formal modeling of biological systems. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan Hardware-in-the-loop model-less diagnostic test generation. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Eman El Mandouh, Amr G. Wassal Estimation of formal verification cost using regression machine learning. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Subarna Sinha, David L. Dill Deciphering cancer biology using boolean methods. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Johannes Schreiner, Rainer Findenig, Wolfgang Ecker Design centric modeling of digital hardware. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Daniela De Venuto, Valerio Francesco Annese, Giovanni Mezzina, Michele Ruta, Eugenio Di Sciascio Brain-computer interface using P300: a gaming approach for neurocognitive impairment diagnosis. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Loïc Besnard, Thierry Gautier, Clément Guy, Paul Le Guernic, Jean-Pierre Talpin, Brian R. Larson, Etienne Borde Formal semantics of behavior specifications in the architecture analysis and design language standard. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xiaojun Sun, Priyank Kalla, Florian Enescu Word-level traversal of finite state machines using algebraic geometry. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Santa Cruz, CA, USA, October 7-8, 2016 Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  BibTeX  RDF
1Michele Lora, Sara Vinco, Franco Fummi A unifying flow to ease smart systems integration. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mahesh Nanjundappa, Anirudh Kaushik, Hiren D. Patel, Sandeep K. Shukla Accelerating SystemC simulations using GPUs. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler Behavior Driven Development for circuit design and verification. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Nicola Nicolici On-chip stimuli generation for post-silicon validation. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou A formal method to improve SystemVerilog functional coverage. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Neil C. Audsley, Ian Gray, Andrea Acquaviva, Ralph Haines ToucHMore toolchain and system software for energy and variability customisation. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Rainer Findenig, Thomas Leitner, Wolfgang Ecker Single-source hardware modeling of different abstraction levels with State Charts. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Freek Verbeek, Julien Schmaltz Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Dogan Ulus, Alper Sen 0001 Using haloes in mixed-signal assertion based verification. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Rolf Drechsler, Ian G. Harris, Robert Wille Generating formal system models from natural language descriptions. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Bijan Alizadeh, Masahiro Fujita A functional test generation technique for RTL datapaths. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Diego Braga, Franco Fummi, Graziano Pravadelli, Sara Vinco The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Romain Lemaire, Sebastien Thuries, Frédéric Heitzmann A flexible modeling environment for a NoC-based multicore architecture. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Andrea Acquaviva Energy aware TLM platform simulation via RTL abstraction. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Olfat El-Mahi, Gabriela Nicolescu, Gilles Pesant, Giovanni Beltrame Embedded system verification through constraint-based scheduling. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hao Zheng 0001, Andrew Price, Chris J. Myers Using decision diagrams to compactly represent the state space for explicit model checking. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Ian G. Harris Automatic generation of Verilog bus transactors from natural language protocol specifications. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir Emulation in post-silicon validation: It's not just for functionality anymore. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Yu Bai 0003, Jens Brandt 0001, Klaus Schneider 0001 Monitoring distributed reactive systems. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012 Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  BibTeX  RDF
1Masahiro Fujita Post-silicon verification and debugging with control flow traces and patchable hardware. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Weiwei Chen 0001, Che-Wei Chang, Xu Han 0002, Rainer Dömer Eliminating race conditions in system-level models by using parallel simulation infrastructure. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Simone Bronuzzi, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli Accurate profiling of oracles for self-checking time-constrained embedded software. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Huy Nguyen, Michael S. Hsiao Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Kanad Basu, Prabhat Mishra, Priyadarsan Patra Constrained signal selection for post-silicon validation. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Sara Vinco UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jinpeng Lv, Priyank Kalla, Florian Enescu Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Min Li 0013, Kelson Gent, Michael S. Hsiao Utilizing GPGPUs for design validation with a modified Ant Colony Optimization. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Zeljko Zilic, Sandeep K. Shukla (eds.) 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011 Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  BibTeX  RDF
1Hansu Cho, Samar Abdi Automatic generation of transducer models for multicore system design. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Matin Hashemi, Soheil Ghiasi Towards scalable utilization of embedded manycores in throughput-sensitive applications. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli Interactive presentation abstract: Reusing of properties after discretization of hybrid automata. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Alexander W. Rath, Volkan Esen, Wolfgang Ecker Analog transaction level modeling. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Mike Gemünde, Jens Brandt 0001, Klaus Schneider 0001 Causality analysis of synchronous programs with refined clocks. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Andrea Pellegrini, Valeria Bertacco Cardio: Adaptive CMPs for reliability through dynamic introspective operation. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Wei Hu, Huy Nguyen, Michael S. Hsiao Sufficiency-based filtering of invariants for Sequential Equivalence Checking. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik SAT-based techniques for determining backbones for post-silicon fault localisation. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Amir Masoud Gharehbaghi, Masahiro Fujita Formal verification guided automatic design error diagnosis and correction of complex processors. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Gunar Schirner Modeling, synthesis, and validation of heterogeneous biomedical embedded systems. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Somnath Banerjee, Tushar Gupta, Saurabh Jain A scalable hybrid verification system based on HDL slicing. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tao Xie 0006, Wolfgang Müller 0003, Florian Letombe IP-XACT based system level mutation testing. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli Interactive presentation abstract: Assertion-based verification in embedded-software design. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Hans Eveking, Tobias Dornes, Martin Schweikert Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Bijan Alizadeh, Masahiro Fujita Modular equivalence verification of polynomial datapaths with multiple word-length operands. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Charalambos Ioannides, Geoff Barrett, Kerstin Eder Introducing XCS to Coverage Directed test Generation. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Frederic Risacher, Kenneth J. Schultz Software agnostic approaches to explore pre-silicon system performance. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Peter Lisherness, Kwang-Ting (Tim) Cheng Coverage discounting: A generalized approach for testbench qualification. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Rajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek An ontology and constraint based approach to cache preloading. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Haiqiong Yao, Hao Zheng 0001, Chris J. Myers State space reductions for scalable verification of asynchronous designs. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Ashvin Dsouza Static analysis of deadends in SVA constraints. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Sumit Ahuja, Wei Zhang, Sandeep K. Shukla System level simulation guided approach to improve the efficacy of clock-gating. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Rishiyur S. Nikhil ESL flows are enabled by high-level synthesis with universality. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Pranav Ashar Clock domain verification challenges and scalable solutions. Search on Bibsonomy HLDVT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
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