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Publications of "Hideharu Amano" ( http://dblp.L3S.de/Authors/Hideharu_Amano )

  Author page on DBLP  Author page in RDF  Community of Hideharu Amano in ASPL-2

Publication years (Num. hits)
1983-1992 (16) 1993-1996 (18) 1997-1999 (21) 2000-2001 (19) 2002-2003 (18) 2004-2005 (33) 2006-2007 (33) 2008 (19) 2009 (22) 2010 (15) 2011 (26) 2012 (21) 2013 (29) 2014 (21) 2015 (23) 2016 (20) 2017 (33) 2018 (23) 2019 (2)
Publication types (Num. hits)
article(94) book(1) incollection(2) inproceedings(312) proceedings(3)
Venues (Conferences, Journals, ...)
FPL(49) IEICE Transactions(33) FPT(32) ASP-DAC(16) COOL Chips(13) ARC(12) CANDAR(11) PDPTA(10) MCSoC(9) NOCS(9) Systems and Computers in Japan(9) IEEE Trans. Parallel Distrib. ...(8) ISPAN(8) ERSA(7) ICPP(7) IPDPS(7) More (+10 of total 108)
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The graphs summarize 112 occurrences of 62 keywords

Results
Found 413 publication records. Showing 412 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano Designing High-Performance Interconnection Networks with Host-Switch Graphs. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Keita Azegami, Hayate Okuhara, Hideharu Amano Body Bias Control for Renewable Energy Source with a High Inner Resistance. Search on Bibsonomy IEEE Trans. Multi-Scale Computing Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Search on Bibsonomy IJNC The full citation details ... 2018 DBLP  BibTeX  RDF
1Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. Search on Bibsonomy IEICE Transactions The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. Search on Bibsonomy IEICE Transactions The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy IEICE Transactions The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hideharu Amano (eds.) Principles and Structures of FPGAs. Search on Bibsonomy 2018 DBLP  DOI  BibTeX  RDF
1Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. Search on Bibsonomy ARC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Kazusa Musha, Tomohiro Kudoh, Hideharu Amano Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. Search on Bibsonomy ARC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. Search on Bibsonomy NOCS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hideki Shimura, Hiroyuki Noda, Hideharu Amano C4: An FPGA-based Compression Algorithm for ExpEther. Search on Bibsonomy CANDAR Workshops The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano k-Optimized Path Routing for High-Throughput Data Center Networks. Search on Bibsonomy CANDAR The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. Search on Bibsonomy CANDAR Workshops The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. Search on Bibsonomy CANDAR Workshops The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. Search on Bibsonomy ReConFig The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. Search on Bibsonomy HEART The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ryosuke Kazami, Hayate Okuhara, Hideharu Amano Design automation methodology of a critical path monitor for adaptive voltage controls. Search on Bibsonomy COOL CHIPS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. Search on Bibsonomy NVMSA The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano Performance Prediction for Large-Scale Heterogeneous Platforms. Search on Bibsonomy FCCM The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Takuya Kojima, Hideharu Amano A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy FPL The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC. Search on Bibsonomy DDECS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. Search on Bibsonomy MCSoC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang The First 25 Years of the FPL Conference: Significant Papers. Search on Bibsonomy TRETS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. Search on Bibsonomy IEICE Transactions The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano A Layout-Oriented Routing Method for Low-Latency HPC Networks. Search on Bibsonomy IEICE Transactions The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. Search on Bibsonomy IEICE Transactions The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova A Case for Uni-directional Network Topologies in Large-Scale Clusters. Search on Bibsonomy CLUSTER The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs. Search on Bibsonomy NOCS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi High-Bandwidth Low-Latency Approximate Interconnection Networks. Search on Bibsonomy HPCA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. Search on Bibsonomy ICPP The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. Search on Bibsonomy VLSI-SoC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Naoki Nishikawa, Hideharu Amano, Keisuke Iwai Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU. Search on Bibsonomy NSS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. Search on Bibsonomy CANDAR The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano Glitch-aware variable pipeline optimization for CGRAs. Search on Bibsonomy ReConFig The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. Search on Bibsonomy HEART The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL. Search on Bibsonomy HEART The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash Panel discussions: "Cool chips for the next decade". Search on Bibsonomy COOL Chips The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano Leveraging asymmetric body bias control for low power LSI design. Search on Bibsonomy COOL Chips The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Keita Azegami, Hayate Okuhara, Hideharu Amano Body bias control for renewable energy source with a high inner resistance. Search on Bibsonomy COOL Chips The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda An inductive-coupling link for 3-D Network-on-Chips. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shinsuke Hamada, Atsushi Koshiba, Mitaro Namiki, Hideharu Amano Building block operating system for 3D stacked computer systems with inductive coupling interconnect. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki Building block multi-chip systems using inductive coupling through chip interface. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano Scalable deep neural network accelerator cores with cubic integration using through chip interface. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani In-switch approximate processing: Delayed tasks management for MapReduce applications. Search on Bibsonomy FPL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano Body bias optimization for variable pipelined CGRA. Search on Bibsonomy FPL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. Search on Bibsonomy FPL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mankit Sit, Ryosuke Kazami, Hideharu Amano FPGA-based accelerator for losslessly quantized convolutional neural networks. Search on Bibsonomy ICFPT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi 3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. Search on Bibsonomy ISPAN-FCST-ISCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. Search on Bibsonomy MCSoC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. Search on Bibsonomy MCSoC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. Search on Bibsonomy ICPADS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi Towards Tightly-coupled Datacenter with Free-space Optical Links. Search on Bibsonomy ICCBDC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh Optical network technologies for HPC: computer-architects point of view. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. Search on Bibsonomy IEICE Transactions The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. Search on Bibsonomy IEICE Transactions The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. Search on Bibsonomy IEICE Transactions The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. Search on Bibsonomy ICIS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano Zynq Cluster for CFD Parametric Survey. Search on Bibsonomy ARC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Satoshi Matsuoka, Hideharu Amano, Kengo Nakajima, Koji Inoue, Tomohiro Kudoh, Naoya Maruyama, Kenjiro Taura, Takeshi Iwashita, Takahiro Katagiri, Toshihiro Hanawa, Toshio Endo From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano On-the-Fly Data Compression/Decompression Mechanism with ExpEther. Search on Bibsonomy CANDAR The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Takuji Mitsuishi, Takahiro Kaneda, Sunao Torii, Hideharu Amano Implementing Breadth-First Search on a Compact Supercomputer Suiren. Search on Bibsonomy CANDAR The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. Search on Bibsonomy CANDAR The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. Search on Bibsonomy CANDAR The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel MuCCRA4-BB: A fine-grained body biasing capable DRP. Search on Bibsonomy COOL Chips The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel Leveraging FDSOI through body bias domain partitioning and bias search. Search on Bibsonomy DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. Search on Bibsonomy A-SSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano Body bias grain size exploration for a coarse grained reconfigurable accelerator. Search on Bibsonomy FPL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. Search on Bibsonomy PDP The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. Search on Bibsonomy FPT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano Trax solver on Zynq using incremental update algorithm. Search on Bibsonomy FPT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment. Search on Bibsonomy MCSoC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Takaaki Miyajima, David B. Thomas, Hideharu Amano Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA. Search on Bibsonomy IJNC The full citation details ... 2015 DBLP  BibTeX  RDF
1Takaaki Miyajima, David B. Thomas, Hideharu Amano A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. Search on Bibsonomy JIP The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. Search on Bibsonomy IEICE Transactions The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. Search on Bibsonomy IEICE Transactions The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano Breadth First Search on Cost-efficient Multi-GPU Systems. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing. Search on Bibsonomy ARC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. Search on Bibsonomy NOCS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. Search on Bibsonomy CANDAR The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. Search on Bibsonomy ReConFig The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. Search on Bibsonomy COOL Chips The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel Fined-grained body biasing for frequency scaling in advanced SOI processes. Search on Bibsonomy COOL Chips The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Philip Heng Wai Leong, Hideharu Amano, Jason Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang Significant papers from the first 25 years of the FPL conference. Search on Bibsonomy FPL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano 7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. Search on Bibsonomy FPL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano Reduction calculator in an FPGA based switching Hub for high performance clusters. Search on Bibsonomy FPL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi Optimized Core-Links for Low-Latency NoCs. Search on Bibsonomy PDP The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano Trax solver on Zynq with Deep Q-Network. Search on Bibsonomy FPT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano 3D Shared Bus Architecture Using Inductive Coupling Interconnect. Search on Bibsonomy MCSoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. Search on Bibsonomy MCSoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi A metamorphotic Network-on-Chip for various types of parallel applications. Search on Bibsonomy ASAP The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
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