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Publications at "IEEE Trans. VLSI Syst."( http://dblp.L3S.de/Venues/IEEE_Trans._VLSI_Syst. )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tvlsi

Publication years (Num. hits)
1993 (59) 1994 (54) 1995 (48) 1996 (46) 1997 (48) 1998 (82) 1999 (56) 2000 (85) 2001 (97) 2002 (98) 2003 (114) 2004 (137) 2005 (140) 2006 (135) 2007 (141) 2008 (176) 2009 (177) 2010 (190) 2011 (240) 2012 (242) 2013 (240) 2014 (273) 2015 (335) 2016 (344) 2017 (333) 2018 (274) 2019 (166)
Publication types (Num. hits)
article(4330)
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Found 4330 publication records. Showing 4330 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Sungju Ryu, Naebeom Park, Jae-Joon Kim Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1P. R. Chithira, Vinita Vasudevan Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nitish Kumar Srivastava, Rajit Manohar Operation-Dependent Frequency Scaling Using Desynchronization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yao Xiao, Shahin Nazarian, Paul Bogdan Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tejinder Singh Sandhu, Kamal El-Sankary Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Omar Elsayed, Jorge Zarate-Roldan, Amr Abuellil, Faisal Abdel-Latif Hussien, Ahmed Eladawy, Edgar Sánchez-Sinencio Highly Linear Low-Power Wireless RF Receiver for WSN. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chih-Wen Lu, Ping-Yeh Yin, Mu-Yong Lin A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luong N. Nguyen, Chia-Lin Cheng, Milos Prvulovic, Alenka G. Zajic Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar 0001 Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sami Salamin, Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tomasz Kulej, Fabian Khateb, Luis H. C. Ferreira A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas Four-Level Forms for Memristive Material Implication Logic. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Suhong Moon, Kwanghyun Shin, Dongsuk Jeon Enhancing Reliability of Analog Neural Network Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hadi Jahanirad CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim A Restore-Free Mode for MLC STT-RAM Caches. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sebastian Huhn 0001, Stefan Frehse, Robert Wille, Rolf Drechsler Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wael Dghais, Malek Souilem, Muhammad Alam Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cheng-En Hsieh, Shen-Iuan Liu A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki An Analog LO Harmonic Suppression Technique for SDR Receivers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yaqub Mahnashi, Fang Z. Peng A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Qiaoyan Yu Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guillaume Renaud, Mamadou Diallo, Manuel J. Barragan, Salvador Mir Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zahi Moudallal, Farid N. Najm Power Scheduling With Active RC Power Grids. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang SLECTS: Slew-Driven Clock Tree Synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Murali K. Rajendran, V. Priya, Shourya Kansal, Gajendranath Chowdary, Ashudeb Dutta A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuan Liang, Chirn Chye Boon, Chenyang Li, Xiao-Lan Tang, Herman Jalli Ng, Dietmar Kissinger, Yong Wang, Qingfeng Zhang, Hao Yu Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xu Fang, Yang Yu, Xiyuan Peng TSV Prebond Test Method Based on Switched Capacitors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fabrizio Riente, Daniel Melis, Marco Vacca Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mario Garrido, Jesús Grajal, Oscar Gustafsson Optimum Circuits for Bit-Dimension Permutations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amin Norollah, Danesh Derafshi, Hakem Beitollahi, Mahdi Fazeli RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Qin Wang, Zechen Liu, Jian-Fei Jiang, Naifeng Jing, Weiguang Sheng A New Cellular-Based Redundant TSV Structure for Clustered Faults. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu An On-Chip Relaxation Oscillator With Comparator Delay Compensation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ding-Yuan Lee, Ching-Che Wang, An-Yeu Wu Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xiang Ge, Fan Yang 0001, Hengliang Zhu, Xuan Zeng 0001, Dian Zhou An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jiangtao Xu, Wei Li 0104, Kaiming Nie, Liqiang Han, Xiyang Zhao A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Safwat Mostafa Noor, Eugene John, Manoj Panday Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yintang Yang, Ke Chen, Huaxi Gu, Bowen Zhang, Lijing Zhu TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dae-Hyun Kim, Shu-Han Hsu, Linda Milor Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi-An Chang, Shen-Iuan Liu A 13.4-MHz Relaxation Oscillator With Temperature Compensation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shirshendu Roy, Debiprasad Priyabrata Acharya, Ajit Kumar Sahoo Low-Complexity Architecture of Orthogonal Matching Pursuit Based on QR Decomposition. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sandhya Koteshwara, Amitabh Das, Keshab K. Parhi Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Thinh Hung Pham, Phong Tran, Siew Kei Lam High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bing Li 0011, Ji-Ping Na, Wei Wang 0165, Jia Liu 0011, Qian Yang, Pui-In Mak A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy 0001, Shreyas Sen Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Manas Kumar Lenka, Gaurab Banerjee A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich A Calibratable Detector for Invasive Attacks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amard Afzalian, Hossein Miar Naimi, Massoud Dousti What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process? Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pavan Kumar Javvaji, Spyros Tragoudas On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott Lerner, Isikcan Yilmaz, Baris Taskin Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianchan Guan, Xiaoyang Zeng, Mingoo Seok Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ricardo Martins 0003, Nuno Lourenço 0003, Nuno Horta, Jun Yin, Pui-In Mak, Rui P. Martins Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shirin Pourashraf, Jaime Ramírez-Angulo, Jose Maria Hinojo Montero, Ramón González Carvajal, Antonio J. López-Martín ±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jakub Siast, Adam Luczak, Marek Domanski RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1ByongChan Lim, Mark Horowitz An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Zhang 0034, Debajit Basak, Kong-Pang Pun Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tutu Wan, Yasha Karimi, Milutin Stanacevic, Emre Salman AC Computing Methodology for RF-Powered IoT Devices. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xunzhao Yin, Xiaoming Chen 0003, Michael T. Niemier, Xiaobo Sharon Hu Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba 0002 Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev A Parametric DFT Scheme for STT-MRAMs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi Estimating and Mitigating Aging Effects in Routing Network of FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Qinghui Hong, Qiujie Wu, Xiaoping Wang, Zhigang Zeng Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Wen, Yuejun Zhang, Xiaoyang Zeng Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Massimo Alioto Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Uthman Alsaiari, Fayez Gebali Hardware Trojan Detection Using Reconfigurable Assertion Checkers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Georgios Zervakis, Konstantina Koliogeorgi, Dimitrios Anagnostos, Nikolaos Zompakis, Kostas Siozios VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Debapriya Basu Roy, Debdeep Mukhopadhyay High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak Design and Optimization of Inductive-Coupling Links for 3-D-ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Duncan J. M. Moss, David Boland, Philip H. W. Leong A Two-Speed, Radix-4, Serial-Parallel Multiplier. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianwen Li, Hongjin Liu, Haigang Yang Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Panagiotis Chaourani, Saul Rodriguez, Per-Erik Hellstrom, Ana Rusu Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1John Vista, Ashish Ranjan A Simple Floating MOS-Memristor for High-Frequency Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Han Zhou, Zeyu Sun, Sheriff Sadiqbatcha, Naehyuck Chang, Sheldon X.-D. Tan EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri Black-Hat High-Level Synthesis: Myth or Reality? Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, Abdelhalim Zekry Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gaurav Saini, Maryam Shojaei Baghini A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shaohan Liu, Dake Liu A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jeetendra Singh, Balwinder Raj Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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