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Publications at "IEEE Trans. VLSI Syst."( http://dblp.L3S.de/Venues/IEEE_Trans._VLSI_Syst. )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tvlsi

Publication years (Num. hits)
1993 (59) 1994 (54) 1995 (48) 1996 (46) 1997 (48) 1998 (82) 1999 (56) 2000 (85) 2001 (97) 2002 (98) 2003 (114) 2004 (137) 2005 (140) 2006 (135) 2007 (141) 2008 (176) 2009 (177) 2010 (190) 2011 (240) 2012 (242) 2013 (240) 2014 (273) 2015 (335) 2016 (344) 2017 (333) 2018 (274) 2019 (258)
Publication types (Num. hits)
article(4422)
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Found 4422 publication records. Showing 4422 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sami Salamin, Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi Estimating and Mitigating Aging Effects in Routing Network of FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Safwat Mostafa Noor, Eugene John, Manoj Panday Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fabrizio Riente, Daniel Melis, Marco Vacca Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tutu Wan, Yasha Karimi, Milutin Stanacevic, Emre Salman AC Computing Methodology for RF-Powered IoT Devices. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar 0001 Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gaurav Saini, Maryam Shojaei Baghini A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianchan Guan, Xiaoyang Zeng, Mingoo Seok Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amin Norollah, Danesh Derafshi, Hakem Beitollahi, Mahdi Fazeli RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Panni Wang, Feng Xu, Bo Wang, Bin Gao 0006, Huaqiang Wu, He Qian, Shimeng Yu Three-Dimensional nand Flash for Vector-Matrix Multiplication. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amandeep Kaur, Deepak Mishra 0003, Mukul Sarkar A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Marco Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Taehui Na, Byungkyu Song, Sara Choi, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han 0001 An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Test Compaction by Test Removal Under Transparent Scan. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Odile Liboiron-Ladouceur, Glenn E. R. Cowan Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Duy Thanh Nguyen, Tuan Nghia Nguyen, Hyun Kim, Hyuk-Jae Lee A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac Modeling and Detectability of Full Open Gate Defects in FinFET Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Eduardo Weber Wächter, Cedric de Bellefroid, Basireddy Karunakar Reddy, Amit Kumar Singh, Bashir M. Al-Hashimi, Geoff V. Merrett Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wael Dghais, Malek Souilem, Muhammad Alam Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rafael Sanchotene Silva, Lucas Pereira Luiz, Márcio Cherem Schneider, Carlos Galup-Montoro A Test Chip for Characterization of the Series Association of MOSFETs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ned Bingham, Rajit Manohar QDI Constant-Time Counters. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1ByongChan Lim, Mark Horowitz An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang SLECTS: Slew-Driven Clock Tree Synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pratheep Bondalapati, Won Namgoong Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang-Bang Digital PLL With Transport Delay Using Fokker-Planck Equations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jakub Siast, Adam Luczak, Marek Domanski RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Zhang 0034, Debajit Basak, Kong-Pang Pun Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xizhu Peng, Jinfeng Guo, Qingqing Bao, Zeyu Li, Haoyu Zhuang, He Tang A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jisu Min, Cheol Kim, Sung-Yong Kim, Kee-Won Kwon A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jeetendra Singh, Balwinder Raj Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tai-Cheng Lee, Yih-Lang Li Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy 0001, Shreyas Sen Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hadi Jahanirad CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Seong-Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Extended Transparent-Scan. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Huanyu Wang, Qihang Shi, Domenic Forte, Mark M. Tehranipoor Probing Assessment Framework and Evaluation of Antiprobing Solutions. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shukla Banik, Suchismita Roy, Bibhash Sen Application-Dependent Testing of FPGA Interconnect Network. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xu Fang, Yang Yu, Xiyuan Peng TSV Prebond Test Method Based on Switched Capacitors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guillaume Renaud, Mamadou Diallo, Manuel J. Barragan, Salvador Mir Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew-Kei Lam, Changhai Ou Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Padding of Multicycle Broadside and Skewed-Load Tests. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Panagiotis Chaourani, Saul Rodriguez, Per-Erik Hellstrom, Ana Rusu Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shuo-Han Chen, Yuan-Hao Chang, Yu-Ming Chang, Wei-Kuan Shih mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM Storages. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek Multiloop Control for Fast Transient DC-DC Converter. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba 0002 Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Lukas Zimmermann, Alexander Scholz, Mehdi Baradaran Tahoori, Jasmin Aghassi-Hagmann, Axel Sikora Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yajuan He, Jiubai Zhang, Xiaoqing Wu, Xin Si, Shaowei Zhen, Bo Zhang 0027 A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1P. R. Chithira, Vinita Vasudevan Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ting-Sheng Chen, Kai-Ni Hou, Win-Ken Beh, An-Yeu Wu Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih 74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi-An Chang, Shen-Iuan Liu A 13.4-MHz Relaxation Oscillator With Temperature Compensation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yufei Ding, Weisheng Zhao, Yuan Xie 0001 DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Prathamesh Khatavkar, Sankaran Aniruddhan 432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yuan Xie 0001, Weisheng Zhao PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shuenn-Yuh Lee, Zhan-Xian Liao, Chih-Hung Lee Energy-Harvesting Circuits With a High-Efficiency Rectifier and a Low Temperature Coefficient Bandgap Voltage Reference. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Massimo Alioto Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang 0001, Dijun Liu, Weisheng Zhao An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shaohan Liu, Dake Liu A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xin Zhan, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li 0001 Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zahi Moudallal, Farid N. Najm Power Scheduling With Active RC Power Grids. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tomasz Kulej, Fabian Khateb, Luis Henrique de Carvalho Ferreira A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Han Zhou, Zeyu Sun, Sheriff Sadiqbatcha, Naehyuck Chang, Sheldon X.-D. Tan EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu An On-Chip Relaxation Oscillator With Comparator Delay Compensation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1C.-J. Richard Shi, Aili Wang Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, José Miguel Rocha-Pérez Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jiangtao Xu, Wei Li 0104, Kaiming Nie, Liqiang Han, Xiyang Zhao A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christopher Cowan Drafting in Self-Timed Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1John Vista, Ashish Ranjan A Simple Floating MOS-Memristor for High-Frequency Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jianwei Liu 0005, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yaqub Mahnashi, Fang Z. Peng A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras Postbond Test of Through-Silicon Vias With Resistive Open Defects. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chih-Wen Lu, Ping-Yeh Yin, Mu-Yong Lin A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Siyuan Xu, Benjamin Carrión Schäfer Toward Self-Tunable Approximate Computing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Qinghui Hong, Qiujie Wu, Xiaoping Wang, Zhigang Zeng Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Aayush Ankit, Minsuk Koo, Shreyas Sen, Kaushik Roy 0001 Powerline Communication for Enhanced Connectivity in Neuromorphic Systems. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abdullah Guler, Niraj K. Jha Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Iman Y. Taha, Mitra Mirhassani A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Andrew J. Douglass, Sunil P. Khatri Fast, Ring-Based Design of 3-D Stacked DRAM. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, Abdelhalim Zekry Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weiqiang Liu, Sailong Fan, Ayesha Khalid, Ciara Rafferty, Máire O'Neill Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuan Dong 0003, Lihong Zhang EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chun-Chi Chen, Chao-Lieh Chen, Yi Lin, Song-Quan You An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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