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Publications at "IEEE Trans. on CAD of Integrated Circuits and Systems"( http://dblp.L3S.de/Venues/IEEE_Trans._on_CAD_of_Integrated_Circuits_and_Systems )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tcad

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article(5491)
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Found 5491 publication records. Showing 5491 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Xiaowen Wang, William H. Robinson Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen, Hsin-Wen Wei, Wei-Kuan Shih Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaewon Jang, Minho Cheong, Sungho Kang TSV Repair Architecture for Clustered Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cunxi Yu, Maciej J. Ciesielski Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Utkarsh Gupta, Priyank Kalla, Vikas Rao Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li 0001, Yiran Chen, Weisheng Zhao Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guoqi Xie, Gang Zeng, Ryo Kurachi, Hiroaki Takada, Zhetao Li, Renfa Li, Keqin Li 0001 WCRT Analysis and Evaluation for Sporadic Message-Processing Tasks in Multicore Automotive Gateways. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuanle Ren, Francisco Pimentel Torres, Ronald D. Blanton, Vítor Grade Tavares IC Protection Against JTAG-Based Attacks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yangdi Lyu, Xiaoke Qin, Mingsong Chen, Prabhat Mishra Directed Test Generation for Validation of Cache Coherence Protocols. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz LFSR-Based Test Generation for Path Delay Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luan H. K. Duong, Peng Yang 0003, Zhifei Wang, Yi-Shing Chang, Jiang Xu 0001, Zhehui Wang, Xuanqi Chen Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Jiangfan Huang, Jing Yang, Tao Li A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, Wen-Zhi Huang OCMAS: Online Page Clustering for Multibank Scratchpad Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jong Hwan Ko, Duckhwan Kim 0001, Taesik Na, Saibal Mukhopadhyay Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott C. Wolfson, Fat D. Ho 2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos Automatic Generation of Peak-Power Traffic for Networks-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaime Octavio Guerra-Pulido, Pablo Roberto Pérez-Alcázar Time-Domain Numerical Simulation of Electronic Circuits and Surface Acoustic Wave Devices Using Their Admittance Parameters. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dawon Park, Younghyun Kim Fast Pareto Front Exploration for Design of Reconfigurable Energy Storage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amina Qureshi, Osman Hasan Formal Probabilistic Analysis of Low Latency Approximate Adders. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jody Maick Matos, Jordi Carrabina, André Inácio Reis Efficiently Mapping VLSI Circuits With Simple Cells. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Xie, Ankur Srivastava Anti-SAT: Mitigating SAT Attack on Logic Locking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Yun Dai, Robert K. Brayton Verification and Synthesis of Clock-Gated Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohsen Imani, Saransh Gupta, Sahil Sharma, Tajana Simunic Rosing NVQuery: Efficient Query Processing in Nonvolatile Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ananya Singla, Varsha Agarwal, Sudip Roy 0001, Arijit Mondal Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anirban Sengupta, Deepak Kachave, Dipanjan Roy Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jin-Tai Yan Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mustafa Efendioglu, Alper Sen 0001, Yavuz Köroglu Bug Prediction of SystemC Models Using Machine Learning. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bijan Alizadeh, Seyyed Reza Sharafinejad Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar An Analytical Approach for Error PMF Characterization in Approximate Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, Yiyu Shi Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1JuHyung Hong, Jeongbin Kim, Sangwoo Han, Eui-Young Chung A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Joydeb Mandal, Mrinal Kanti Mandal Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Feilong Zhang, Chenkun Wang, Fei Lu 0004, Qi Chen, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yun Cheng, Huawei Li, Ying Wang 0001, Xiaowei Li 0001 Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto Logic Synthesis for Interpolant Circuit Compaction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Grace Li Zhang, Bing Li 0005, Yiyu Shi, Jiang Hu, Ulf Schlichtmann EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Hsuan Su, Yao-Wen Chang DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Mingxu Zhang, Xuan Yang, Tao Li A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wenhui Zhang, Qiang Cao, Zhonghai Lu Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Siqi Wang, Gayathri Ananthanarayanan, Tulika Mitra OPTiC: Optimizing Collaborative CPU-GPU Computing on Mobile Devices With Thermal Constraints. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sudip Poddar, Sukanta Bhattacharjee, Subhas C. Nandy, Krishnendu Chakrabarty, Bhargab B. Bhattacharya Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fuyang Li, Keni Qiu, Mengying Zhao, Jingtong Hu, Yongpan Liu, Yong Guan, Chun Jason Xue Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang 0002, Yuan Xie 0001, Huazhong Yang GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weichen Liu, Juan Yi, Mengquan Li, Peng Chen, Lei Yang 0018 Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar Dynamic Approximation of JPEG Hardware. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maoxiang Yi, Jingchang Bian, Tianming Ni, Cuiyun Jiang, Hao Chang, Huaguo Liang A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nitin Rathi, Priyadarshini Panda, Kaushik Roy 0001 STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Diagnostic Test Generation That Addresses Diagnostic Holes. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Max Willsey, Vincent T. Lee, Alvin Cheung, Rastislav Bodík, Luis Ceze Iterative Search for Reconfigurable Accelerator Blocks With a Compiler in the Loop. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Matthew Layne Beckler, Ronald D. Blanton On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Eric Schneider, Hans-Joachim Wunderlich SWIFT: Switch-Level Fault Simulation on GPUs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Philip Brisk, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatié, Swaroop Ghosh, Xun Jiao TCAD EIC Message: February 2019. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Timo Feld, Frank Slomka Exact Interference of Tasks With Variable Rate-Dependent Behavior. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jorge Martinez 0003, Ignacio Sanudo Olmedo, Marko Bertogna Analytical Characterization of End-to-End Communication Delays With Logical Execution Time. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sobhan Niknam, Peng Wang 0036, Todor Stefanov Resource Optimization for Real-Time Streaming Applications Using Task Replication. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Zhenya Zhang, Gidon Ernst, Sean Sedwards, Paolo Arcaini, Ichiro Hasuo Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Congming Gao, Liang Shi, Cheng Ji, Yejia Di, Kaijie Wu 0001, Chun Jason Xue, Edwin Hsing-Mean Sha Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hassaan Saadat, Haseeb Bokhari, Sri Parameswaran Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mehran Mozaffari Kermani, Amir Jalali, Reza Azarderakhsh, Jiafeng Xie, Kim-Kwang Raymond Choo Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri Secure Randomized Checkpointing for Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yilei Li, Kirti Dhwaj, Chien-Heng Wong, Yuan Du, Li Du, Yiwu Tang, Yiyu Shi, Tatsuo Itoh, Mau-Chung Frank Chang A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yifan Zhang 0005, Zhengfeng Yang, Wang Lin, Huibiao Zhu, Xin Chen 0027, Xuandong Li Safety Verification of Nonlinear Hybrid Systems Based on Bilinear Programming. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sudipta Chattopadhyay 0001, Abhik Roychoudhury Symbolic Verification of Cache Side-Channel Freedom. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Paolo Maffezzoni, Zheng Zhang 0005, Salvatore Levantino, Luca Daniel Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Olga Krestinskaya, Timur Ibrayev, Alex Pappachen James Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Panagiotis Georgiou, Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty Testing 3D-SoCs Using 2-D Time-Division Multiplexing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Wei-Che Wang, Charles Zhao, Puneet Gupta Assessing Layout Density Benefits of Vertical Channel Devices. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Minhui Zou, Xiaotong Cui, Liang Shi, Kaijie Wu 0001 Potential Trigger Detection for Hardware Trojans. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hayoung Lee, Kiwon Cho, Donghyun Kim, Sungho Kang Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Chih-Hao Wang, Tong-Yu Hsieh On Probability of Detection Lossless Concurrent Error Detection Based on Implications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Le Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Dihu Chen, Zixin Wang Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Chenchen Fu, Peng Wu 0009, Minming Li, Chun Jason Xue, Yingchao Zhao, Song Han Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jea Woo Park, Andres Torres, Xiaoyu Song Litho-Aware Machine Learning for Hotspot Detection. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hao Li, Xiaowei Liu, Fanshu Jiao, Alex Doboli, Simona Doboli InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for Analog Circuit Design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alwin Zulehner, Robert Wille One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fanruo Meng, Yuan Xue, Chengmo Yang Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Chen Yang 0005, Shouyi Yin, Shaojun Wei CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jin Miao, Meng Li 0004, Subhendu Roy, Yuzhe Ma, Bei Yu 0001 SD-PUF: Spliced Digital Physical Unclonable Function. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Wenmian Hua, Rajit Manohar Exact Timing Analysis for Asynchronous Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Cheng Ji, Li-Pin Chang, Chao Wu, Liang Shi, Chun Jason Xue An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yibo Lin, Bei Yu 0001, Meng Li 0004, David Z. Pan Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Wuxi Li, Shounak Dhar, David Z. Pan UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Lingtai Wang, Naijun Zhan, Jie An The Opacity of Real-Time Automata. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ali Pahlevan, Xiaoyu Qu, Marina Zapater, David Atienza Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yixiao Ding, Chris Chu, Wai-Kei Mak Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
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