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Publications at "IEEE Trans. on CAD of Integrated Circuits and Systems"( http://dblp.L3S.de/Venues/IEEE_Trans._on_CAD_of_Integrated_Circuits_and_Systems )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tcad

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Publication types (Num. hits)
article(5585)
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Found 5585 publication records. Showing 5585 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott C. Wolfson, Fat D. Ho 2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daniele Jahier Pagliari, Yves Durand, David Coriat, Edith Beigné, Enrico Macii, Massimo Poncino Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kai Huang 0002, Xiaomeng Zhang, Dan-dan Zheng, Min Yu, Xiaowen Jiang, Xiaolang Yan, Lisane B. de Brisolara, Ahmed Amine Jerraya A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Keith A. Campbell, Chen-Hsuan Lin, Deming Chen Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Diagnostic Test Generation That Addresses Diagnostic Holes. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ricardo Martins 0003, Nuno Lourenço 0003, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhe Li 0001, Ji Li 0006, Ao Ren, Ruizhe Cai, Caiwen Ding, Xuehai Qian, Jeffrey Draper, Bo Yuan 0001, Jian Tang 0008, Qinru Qiu, Yanzhi Wang HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Skewed-Load Tests for Transition and Stuck-at Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaime Octavio Guerra-Pulido, Pablo Roberto Pérez-Alcázar Time-Domain Numerical Simulation of Electronic Circuits and Surface Acoustic Wave Devices Using Their Admittance Parameters. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Han-Yi Lin, Jen-Wei Hsieh Revive Bad Flash-Memory Pages by HLC Scheme. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jong Hwan Ko, Duckhwan Kim 0001, Taesik Na, Saibal Mukhopadhyay Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1JuHyung Hong, Jeongbin Kim, Sangwoo Han, Eui-Young Chung A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Meng Li 0004, Bei Yu 0001, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner Alleviating Scalability Limitation of Accelerator-Based Platforms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Jiangfan Huang, Jing Yang, Tao Li A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Xie, Ankur Srivastava Anti-SAT: Mitigating SAT Attack on Logic Locking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuda Zhou, Zidong Du, Shijin Zhang, Lei Zhang, Huiying Lan, Shaoli Liu, Ling Li 0001, Qi Guo, Tianshi Chen, Yunji Chen Addressing Sparsity in Deep Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maoxiang Yi, Jingchang Bian, Tianming Ni, Cuiyun Jiang, Hao Chang, Huaguo Liang A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sakari Lahti, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen Are We There Yet? A Study on the State of High-Level Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, Yiyu Shi Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jin-Tai Yan Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weichen Liu, Juan Yi, Mengquan Li, Peng Chen 0027, Lei Yang 0018 Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Mingxu Zhang, Xuan Yang, Tao Li A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jody Maick Matos, Jordi Carrabina, André Inácio Reis Efficiently Mapping VLSI Circuits With Simple Cells. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhongyuan Tian, Zhe Wang 0003, Jiang Xu 0001, Haoran Li, Peng Yang 0003, Rafael Kioji Vivas Maeda Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Philip Brisk, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatié, Swaroop Ghosh, Xun Jiao TCAD EIC Message: February 2019. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wei Jiang, Xiong Pan, Ke Jiang, Liang Wen, Qi Dong Energy-Aware Design of Stochastic Applications With Statistical Deadline and Reliability Guarantees. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar An Analytical Approach for Error PMF Characterization in Approximate Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sudip Poddar, Sukanta Bhattacharjee, Subhas C. Nandy, Krishnendu Chakrabarty, Bhargab B. Bhattacharya Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tao Yang, Yadong Wei, Zhijun Tu, Haolun Zeng, Michel A. Kinsy, Nanning Zheng, Pengju Ren Design Space Exploration of Neural Network Activation Function Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Song Chen 0001, Qi Xu, Bei Yu 0001 Adaptive 3D-IC TSV Fault Tolerance Structure Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nitin Rathi, Priyadarshini Panda, Kaushik Roy 0001 STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Iraj Moghaddasi, Arash Fouman, Mostafa E. Salehi, Mehdi Kargahi Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xiaowei Xu 0004, Feng Lin 0004, Wenyao Xu, Xin-Wei Yao, Yiyu Shi, Dewen Zeng, Yu Hu MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Carna Zivkovic, Christoph Grimm 0001, Markus Olbrich, Oliver Scharf, Erich Barke Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuan Du, Li Du, Xuefeng Gu, Jieqiong Du, X. Shawn Wang, Boyu Hu, Mingzhe Jiang, Xiaoliang Chen, Subramanian S. Iyer, Mau-Chung Frank Chang An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xin Zhan, Peng Li 0001, Edgar Sánchez-Sinencio Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli LUT-Based Hierarchical Reversible Logic Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Eric Schneider, Hans-Joachim Wunderlich SWIFT: Switch-Level Fault Simulation on GPUs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shayan Tabatabaei Nikkhah, Mahdi Zahedi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Derong Liu 0002, Bei Yu 0001, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abdullah Yesil, Yunus Babacan, Firat Kaçar Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xiaowen Wang, William H. Robinson Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alwin Zulehner, Alexandru Paler, Robert Wille An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Joydeb Mandal, Mrinal Kanti Mandal Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu 0001, Evangeline F. Y. Young Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhijing Li, Zhao Chen 0004, Yili Zhang, Zixin Huang, Weikang Qian Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Feilong Zhang, Chenkun Wang, Fei Lu 0004, Qi Chen 0008, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xueyan Wang, Qiang Zhou 0001, Yici Cai, Gang Qu Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Keith A. Campbell, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada Logic BIST With Capture-Per-Clock Hybrid Test Points. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Changho Han, Andrew B. Kahng, Lutong Wang, Bangqi Xu Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ananya Singla, Varsha Agarwal, Sudip Roy 0001, Arijit Mondal Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bijan Alizadeh, Seyyed Reza Sharafinejad Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Onur Sahin, Lothar Thiele, Ayse K. Coskun Maestro: Autonomous QoS Management for Mobile Applications Under Thermal Constraints. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie 0001, Yu Wang 0002, Huazhong Yang TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar Dynamic Approximation of JPEG Hardware. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sukanta Bhattacharjee, Ansuman Banerjee, Tsung-Yi Ho, Krishnendu Chakrabarty, Bhargab B. Bhattacharya Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuanle Ren, Francisco Pimentel Torres, Ronald D. Blanton, Vítor Grade Tavares IC Protection Against JTAG-Based Attacks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christian Pilato, Kaijie Wu 0001, Siddharth Garg, Ramesh Karri, Francesco Regazzoni TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shengcheng Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohammed Shayan, Jack Tang, Krishnendu Chakrabarty, Ramesh Karri Security Assessment of Micro-Electrode-Dot-Array Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bart Plovie, Jan Vanfleteren, Thomas Vervust, Andrés Vásquez Quintero, Frederick Bossuyt Design Automation of Meandered Interconnects for Stretchable Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Utkarsh Gupta, Priyank Kalla, Vikas Rao Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen, Hsin-Wen Wei, Wei-Kuan Shih Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christine S. Chan, Alper Sinan Akyürek, Baris Aksanli, Tajana Simunic Rosing Optimal Performance-Aware Cooling on Enterprise Servers. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz LFSR-Based Test Generation for Path Delay Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cheng Zhuo, Kassan Unda, Yiyu Shi, Wei-Kai Shih From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alwin Zulehner, Robert Wille Advanced Simulation of Quantum Computations. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Woojoo Lee, Taewook Kang, Jae-Jin Lee, Kyuseung Han, Joongheon Kim, Massoud Pedram TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guoqi Xie, Gang Zeng, Ryo Kurachi, Hiroaki Takada, Zhetao Li, Renfa Li, Keqin Li 0001 WCRT Analysis and Evaluation for Sporadic Message-Processing Tasks in Multicore Automotive Gateways. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Hsuan Su, Yao-Wen Chang DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Grace Li Zhang, Bing Li 0005, Yiyu Shi, Jiang Hu, Ulf Schlichtmann EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner Verification at RTL Using Separation of Design Concerns. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yun Cheng, Huawei Li, Ying Wang 0001, Xiaowei Li 0001 Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yaguang Li, Cheng Zhuo, Pingqiang Zhou A Cross-Layer Framework for Temporal Power and Supply Noise Prediction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Antara Ain, Pallab Dasgupta Interpreting Local Variables in AMS Assertions During Simulation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaewon Jang, Minho Cheong, Sungho Kang TSV Repair Architecture for Clustered Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yibo Lin, Meng Li 0004, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos Automatic Generation of Peak-Power Traffic for Networks-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong DtCraft: A High-Performance Distributed Execution Engine at Scale. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Wang, Ping Lv, Leibo Liu, Jie Han 0001, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sudip Poddar, Robert Wille, Hafizur Rahaman, Bhargab B. Bhattacharya Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liying Li, Peijin Cong, Kun Cao, Junlong Zhou, Tongquan Wei, Mingsong Chen, Shiyan Hu, Xiaobo Sharon Hu Game Theoretic Feedback Control for Reliability Enhancement of EtherCAT-Based Networked Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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