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Publications at "IEEE Trans. on CAD of Integrated Circuits and Systems"( http://dblp.L3S.de/Venues/IEEE_Trans._on_CAD_of_Integrated_Circuits_and_Systems )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tcad

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article(5554)
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Found 5554 publication records. Showing 5554 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Xiaowen Wang, William H. Robinson Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen, Hsin-Wen Wei, Wei-Kuan Shih Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bo Mao, Jindong Zhou, Suzhen Wu, Hong Jiang 0001, Xiao Chen, Weijian Yang Improving Flash Memory Performance and Reliability for Smartphones With I/O Deduplication. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Suhyeong Choi, Seongbo Shim, Youngsoo Shin Neural Network Classifier-Based OPC With Imbalanced Training Data. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alwin Zulehner, Alexandru Paler, Robert Wille An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaewon Jang, Minho Cheong, Sungho Kang TSV Repair Architecture for Clustered Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark Mohammad Tehranipoor Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cunxi Yu, Maciej J. Ciesielski Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rickard Ewetz, Cheng-Kok Koh Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Utkarsh Gupta, Priyank Kalla, Vikas Rao Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li 0001, Yiran Chen, Weisheng Zhao Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhijing Li, Zhao Chen, Yili Zhang, Zixin Huang, Weikang Qian Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Guoqi Xie, Gang Zeng, Ryo Kurachi, Hiroaki Takada, Zhetao Li, Renfa Li, Keqin Li 0001 WCRT Analysis and Evaluation for Sporadic Message-Processing Tasks in Multicore Automotive Gateways. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xuanle Ren, Francisco Pimentel Torres, Ronald D. Blanton, Vítor Grade Tavares IC Protection Against JTAG-Based Attacks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yangdi Lyu, Xiaoke Qin, Mingsong Chen, Prabhat Mishra Directed Test Generation for Validation of Cache Coherence Protocols. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz LFSR-Based Test Generation for Path Delay Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Qinghui Hong, Ya Li, Xiaoping Wang, Zhigang Zeng A Versatile Pulse Control Method to Generate Arbitrary Multidirection Multibutterfly Chaotic Attractors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luan H. K. Duong, Peng Yang 0003, Zhifei Wang, Yi-Shing Chang, Jiang Xu 0001, Zhehui Wang, Xuanqi Chen Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sakari Lahti, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen Are We There Yet? A Study on the State of High-Level Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Keith A. Campbell, Chen-Hsuan Lin, Deming Chen Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Iraj Moghaddasi, Arash Fouman, Mostafa E. Salehi, Mehdi Kargahi Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Jiangfan Huang, Jing Yang, Tao Li A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shayan Tabatabaei Nikkhah, Mahdi Zahedi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, Wen-Zhi Huang OCMAS: Online Page Clustering for Multibank Scratchpad Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Suzhen Wu, Haijun Li, Bo Mao, Xiaoxi Chen, Kuan-Ching Li Overcome the GC-Induced Performance Variability in SSD-Based RAIDs With Request Redirection. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jong Hwan Ko, Duckhwan Kim 0001, Taesik Na, Saibal Mukhopadhyay Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott C. Wolfson, Fat D. Ho 2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos Automatic Generation of Peak-Power Traffic for Networks-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaime Octavio Guerra-Pulido, Pablo Roberto Pérez-Alcázar Time-Domain Numerical Simulation of Electronic Circuits and Surface Acoustic Wave Devices Using Their Admittance Parameters. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zois-Gerasimos Tasoulas, Iraklis Anagnostopoulos, Lazaros Papadopoulos, Dimitrios Soudris A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas Effective Logic Synthesis for Threshold Logic Circuit Design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato Scaling Up Modulo Scheduling for High-Level Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dawon Park, Younghyun Kim Fast Pareto Front Exploration for Design of Reconfigurable Energy Storage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada Logic BIST With Capture-Per-Clock Hybrid Test Points. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amina Qureshi, Osman Hasan Formal Probabilistic Analysis of Low Latency Approximate Adders. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shiping Wen, Shuixin Xiao, Yin Yang, Zheng Yan 0001, Zhigang Zeng, Tingwen Huang Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jody Maick Matos, Jordi Carrabina, André Inácio Reis Efficiently Mapping VLSI Circuits With Simple Cells. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Andreas Grimmer, Werner Haselmayr, Robert Wille Automated Dimensioning of Networked Labs-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Xie, Ankur Srivastava Anti-SAT: Mitigating SAT Attack on Logic Locking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Yun Dai, Robert K. Brayton Verification and Synthesis of Clock-Gated Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohsen Imani, Saransh Gupta, Sahil Sharma, Tajana Simunic Rosing NVQuery: Efficient Query Processing in Nonvolatile Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ananya Singla, Varsha Agarwal, Sudip Roy 0001, Arijit Mondal Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Antara Ain, Pallab Dasgupta Interpreting Local Variables in AMS Assertions During Simulation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anirban Sengupta, Deepak Kachave, Dipanjan Roy Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu 0001, Evangeline F. Y. Young Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Derong Liu 0002, Bei Yu 0001, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jin-Tai Yan Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mustafa Efendioglu, Alper Sen 0001, Yavuz Köroglu Bug Prediction of SystemC Models Using Machine Learning. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bijan Alizadeh, Seyyed Reza Sharafinejad Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kun Cao, Junlong Zhou, Peijin Cong, Liying Li, Tongquan Wei, Mingsong Chen, Shiyan Hu, Xiaobo Sharon Hu Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar An Analytical Approach for Error PMF Characterization in Approximate Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xiaowei Xu 0004, Feng Lin 0004, Wenyao Xu, Xin-Wei Yao, Yiyu Shi, Dewen Zeng, Yu Hu MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuanwen Huang, Prabhat Mishra Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nasibeh Teimouri, Hamed Tabkhi, Gunar Schirner Alleviating Scalability Limitation of Accelerator-Based Platforms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wei-Ming Chen, Sheng-Wei Cheng, Pi-Cheng Hsiu A User-Centric CPU-GPU Governing Framework for 3-D Mobile Games. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri Translation Validation of Code Motion Transformations Involving Loops. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhe Li 0001, Ji Li 0006, Ao Ren, Ruizhe Cai, Caiwen Ding, Xuehai Qian, Jeffrey Draper, Bo Yuan 0001, Jian Tang 0008, Qinru Qiu, Yanzhi Wang HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, Yiyu Shi Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weijun Zhu, Gang Dong, Yintang Yang Thermal-Aware Modeling and Analysis for a Power Distribution Network Including Through-Silicon-Vias in 3-D ICs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery Timing-Driven and Placement-Aware Multibit Register Composition. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Weiwen Jiang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Lei Yang 0018, Xianzhang Chen, Jingtong Hu On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1JuHyung Hong, Jeongbin Kim, Sangwoo Han, Eui-Young Chung A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Joydeb Mandal, Mrinal Kanti Mandal Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Wei Jiang, Xiong Pan, Ke Jiang, Liang Wen, Qi Dong Energy-Aware Design of Stochastic Applications With Statistical Deadline and Reliability Guarantees. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Feilong Zhang, Chenkun Wang, Fei Lu 0004, Qi Chen 0008, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yun Cheng, Huawei Li, Ying Wang 0001, Xiaowei Li 0001 Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng 0001, Xin Li 0001 Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto Logic Synthesis for Interpolant Circuit Compaction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ricardo Martins 0003, Nuno Lourenço 0003, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhongyuan Tian, Zhe Wang 0003, Jiang Xu 0001, Haoran Li, Peng Yang 0003, Rafael Kioji Vivas Maeda Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sugil Lee, Daewoo Kim, Dong Nguyen, Jongeun Lee Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Grace Li Zhang, Bing Li 0005, Yiyu Shi, Jiang Hu, Ulf Schlichtmann EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christian Pilato, Kaijie Wu 0001, Siddharth Garg, Ramesh Karri, Francesco Regazzoni TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abdullah Yesil, Yunus Babacan, Firat Kaçar Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Hsuan Su, Yao-Wen Chang DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yi Wang 0003, Mingxu Zhang, Xuan Yang, Tao Li A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xin Zhan, Peng Li 0001, Edgar Sánchez-Sinencio Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sukanta Bhattacharjee, Ansuman Banerjee, Tsung-Yi Ho, Krishnendu Chakrabarty, Bhargab B. Bhattacharya Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie 0001, Yu Wang 0002, Huazhong Yang TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner Verification at RTL Using Separation of Design Concerns. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Song Chen 0001, Qi Xu, Bei Yu 0001 Adaptive 3D-IC TSV Fault Tolerance Structure Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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