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Publications at "IPSJ Trans. System LSI Design Methodology"( http://dblp.L3S.de/Venues/IPSJ_Trans._System_LSI_Design_Methodology )

URL (DBLP): http://dblp.uni-trier.de/db/journals/ipsj

Publication years (Num. hits)
2008-2009 (35) 2010 (24) 2011 (18) 2012-2013 (30) 2014-2015 (28) 2016-2017 (17) 2018-2019 (17)
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article(169)
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Found 169 publication records. Showing 169 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Hiroki Koyasu, Yasuhiro Takahashi Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kenshu Seto Scalar Replacement with Circular Buffers. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa An FPGA Implementation Method based on Distributed-register Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yang Liu 0001, Lin Meng, Hiroyuki Tomiyama A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nozomu Togawa Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Takafumi Miyazaki, Shunsuke Takai, Ittetsu Taniguchi, Hiroyuki Tomiyama An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chaofei Yang, Ximing Qiao, Yiran Chen Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1A. K. M. Mahfuzul Islam, Hidetoshi Onodera Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bing Li 0005, Masanori Hashimoto, Ulf Schlichtmann From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nozomu Togawa Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Daisuke Oku, Masao Yanagisawa, Nozomu Togawa Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler Behaviour Driven Development for Hardware Design. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Kenshu Seto Scalar Replacement with Polyhedral Model. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ahmed Awad, Atsushi Takahashi 0001, Satoshi Tanaka, Chikaaki Kodama Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Qian Zhao 0001, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiaoqing Xu, David Z. Pan Toward Unidirectional Routing Closure in Advanced Technology Nodes. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yusuke Matsunaga An Accelerating Technique for SAT-based ATPG. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nozomu Togawa Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ri Cui, Kazuteru Namba A Calibration Technique for DVMC with Delay Time Controllable Inverter. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Atsushi Hashimoto, Nagisa Ishiura Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Michitarou Yabuuchi, Kazutoshi Kobayashi Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Wing-Kai Chow, Evangeline F. Y. Young Placement: From Wirelength to Detailed Routability. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nozomu Togawa Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nana Sutisna, Reina Hongyo, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amro Awad, Ganesh Balakrishnan, Yipeng Wang, Yan Solihin Accurate Cloning of the Memory Access Behavior. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Tulika Mitra Heterogeneous Multi-core Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Lian Zeng, Xin Jiang, Takahiro Watanabe A Performance Enhanced Dual-switch Network-on-chip Architecture. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yusaku Hirai, Shinya Yano, Toshimasa Matsuoka A Delta-Sigma ADC with Stochastic Quantization. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ran Zhang 0005, Tieyuan Pan, Li Zhu, Takahiro Watanabe Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie 0001 Memory and Storage System Design with Nonvolatile Memory Technologies. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Hiroyuki Tomiyama Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell High-level Synthesis for Low-power Design. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Takaaki Miyajima, David B. Thomas, Hideharu Amano Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Motoki Amagasaki, Qian Zhao 0001, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi A 3D FPGA Architecture to Realize Simple Die Stacking. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Matthias Jung 0001, Christian Weis, Norbert Wehn DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Hiroyuki Tomiyama Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang 0002, Fangming Ye Test and Design-for-Testability Solutions for 3D Integrated Circuits. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Hao Zhang 0020, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jingcheng Zhuang, Robert Bogdan Staszewski All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Tsung-Yi Ho Design Automation for Digital Microfluidic Biochips. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Xin Jiang, Lian Zeng, Takahiro Watanabe A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yuta Hagio, Masao Yanagisawa, Nozomu Togawa A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Shingo Kusakabe, Kenshu Seto Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Jörg Bormann, Markus Wedler, Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz A New Formal Verification Approach for Hardware-dependent Embedded System Software. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yuta Kato, Kenshu Seto Loop Fusion with Outer Loop Shifting for High-level Synthesis. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Sangyoung Park, Younghyun Kim, Jaehyun Park, Naehyuck Chang Power Converter-aware Design of Electronics Systems. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yiqiang Sheng, Atsushi Takahashi 0001 A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Amila Akagic, Hideharu Amano Design and Implementation of IP-based iSCSI Offload Engine on an FPGA. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yoonmyung Lee, Dongmin Yoon, Yejoong Kim, David T. Blaauw, Dennis Sylvester Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Huang-Chih Kuo, Youn-Long Lin VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto An FPGA Implementation of a HOG-based Object Detection Processor. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kazuhito Ito, Kazuhiko Kameda A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Xin Jiang, Ran Zhang 0005, Takahiro Watanabe An Efficient Algorithm for 3D NoC Architecture Optimization. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hiroyuki Tomiyama Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Taiga Takata, Yusuke Matsunaga A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Tan Yan, Qiang Ma 0002, Martin D. F. Wong Advances in PCB Routing. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa Energy-efficient High-level Synthesis for HDR Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hiroyuki Tomiyama Message from the Editor-in-Chief. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada A Fast Performance Estimation Framework for System-Level Design Space Exploration. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto DVB-T2 LDPC Decoder with Perfect Conflict Resolution. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Sungho Park, Ahmed Al-Maashri, Kevin M. Irick, Aarti Chandrashekhar, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Vijaykrishnan Narayanan System-On-Chip for Biologically Inspired Vision Applications. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Michitarou Yabuuchi, Kazutoshi Kobayashi NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Walid Lafi, Didier Lattard, Ahmed Amine Jerraya A Stackable LTE Chip for Cost-effective 3D Systems. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang 0007 Robust System Design. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki Scan Vulnerability in Elliptic Curve Cryptosystems. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Hirotaka Kawashima, Naofumi Takagi Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Arda Karaduman, Iver Stubdal, Hideharu Amano Design and Implementation of Echo Instructions for an Embedded Processor. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
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