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Publications of "Ignacio Algredo-Badillo" ( http://dblp.L3S.de/Authors/Ignacio_Algredo-Badillo )

  Author page on DBLP  Author page in RDF  Community of Ignacio Algredo-Badillo in ASPL-2

Publication years (Num. hits)
2006-2015 (15) 2017-2019 (6)
Publication types (Num. hits)
article(13) inproceedings(8)
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Found 22 publication records. Showing 21 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ignacio Algredo-Badillo, Luis A. Morales Rosales, Carlos Arturo Hernández-Gracidas, Juan C. Cruz-Victoria, Daniel Pacheco Bautista, Miguel Morales-Sandoval Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety. Search on Bibsonomy Journal of Intelligent and Fuzzy Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kelsey A. Ramírez-Gutiérrez, Alejandro Medina-Santiago, Alfonso Martinez Cruz, Ignacio Algredo-Badillo, Hayde Peregrina-Barreto Eggshell deformation detection applying computer vision. Search on Bibsonomy Computers and Electronics in Agriculture The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alejandro Medina-Santiago, Mario Alfredo Reyes-Barranca, Ignacio Algredo-Badillo, Alfonso Martinez Cruz, Kelsey A. Ramírez-Gutiérrez, Eleazar Adrián Cortés-Barrón Reconfigurable arithmetic logic unit designed with threshold logic gates. Search on Bibsonomy IET Circuits, Devices & Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luis A. Morales Rosales, Ignacio Algredo-Badillo, Carlos Arturo Hernández-Gracidas, Hector Rodriguez Rangel, Mariana Lobato Báez On-road obstacle detection video system for traffic accident prevention. Search on Bibsonomy Journal of Intelligent and Fuzzy Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Francisco Rubén Castillo Soria, Kelsey A. Ramírez-Gutiérrez, Luis A. Morales Rosales, Alejandro Medina-Santiago, Claudia Feregrino Uribe Lightweight Security Hardware Architecture Using DWT and AES Algorithms. Search on Bibsonomy IEICE Transactions The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1L. Rodriguez-Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. Search on Bibsonomy LASCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1M. A. Saldaña-O., Luis Enrique Ramos Velasco, J. P. Ordaz-O., Abel García-Barrientos, Ignacio Algredo-Badillo, Jean-François Balmat, Frédéric Lafont A comparative study of the wavenet PID controllers for applications in non-linear systems. Search on Bibsonomy CCE The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Search on Bibsonomy Computers & Electrical Engineering The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. Search on Bibsonomy ReCoSoC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ernesto Cortés Pérez, Ignacio Algredo-Badillo, Víctor Hugo García Rodríguez Performance Analysis of ANFIS in short term Wind Speed Prediction Search on Bibsonomy CoRR The full citation details ... 2012 DBLP  BibTeX  RDF
1Francisco Rubén Castillo Soria, Gustavo Fernández Torres, Ignacio Algredo-Badillo A Lossless Data Hiding Technique based on AES-DWT Search on Bibsonomy CoRR The full citation details ... 2012 DBLP  BibTeX  RDF
1Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. Search on Bibsonomy ISVLSI The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. Search on Bibsonomy DSD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Search on Bibsonomy Computers & Electrical Engineering The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. Search on Bibsonomy Journal of Circuits, Systems, and Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Search on Bibsonomy Computers & Electrical Engineering The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. Search on Bibsonomy ENC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. Search on Bibsonomy IEICE Transactions The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. Search on Bibsonomy ReConFig The full citation details ... 2008 DBLP  DOI  BibTeX  RDF AES-CCM, Wireless Networks, FPGA Implementation
1Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. Search on Bibsonomy ICCSA (3) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
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