Search results for "Int. J. Reconfig. Comp."

Hits ?▲	Authors	Title	Venue	Year	Link
1	Nitish Das, P. Aruna Priya	FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Gianmarco Dinelli, Gabriele Meoni, Emilio Rapuano, Gionata Benelli, Luca Fanucci	An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Michael Kirchhoff, Philipp Kerling, Detlef Streitferdt, Wolfgang Fengler 0001	A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Naveed Mahmud, Esam El-Araby	Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Farnam Khalili, Marco Procaccini	Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS).	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Karim M. A. Ali, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser	ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Kizheppatt Vipin	AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Hamish J. Macintosh, Jasmine Banks, Neil A. Kelson	Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Ting Zhang, Bin Liu 0001	Exposing End-to-End Delay in Software-Defined Networking.	Int. J. Reconfig. Comp.	2019	DBLP DOI BibTeX RDF
1	Faisal Mahmood, Mart Toots, Lars-Göran Öfverstedt, Ulf Skoglund	Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Ka Fai Cedric Yiu, Siow Yong Low	On a Real-Time Blind Signal Separation Noise Reduction System.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Lilia Kechiche, Lamjed Touil, Bouraoui Ouni	Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Bruno da Silva, An Braeken, Federico Domínguez, Abdellah Touhafi	Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Gary Gréwal	Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm".	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly	Corrigendum to "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability".	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal	Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization".	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei 0001, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, Huazhong Yang	Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Qianqiao Chen, Vaibhawa Mishra, José Núñez-Yáñez, Georgios Zervas	Reconfigurable Network Stream Processing on Virtualized FPGA Resources.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Bahram N. Uchevler, Kjetil Svarstad	Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin	RP-Ring: A Heterogeneous Multi-FPGA Accelerator.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Nitish Das, P. Aruna Priya	FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method.	Int. J. Reconfig. Comp.	2018	DBLP DOI BibTeX RDF
1	Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic	FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Satheesh Bojja Venkatakrishnan, Elias A. Alwan, John L. Volakis	Challenges in Clock Synchronization for On-Site Coding Digital Beamformer.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs	Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Aous H. Kurdi, Janos L. Grantner, Ikhlas Abdel-Qader	Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini	Efficient Realization of BCD Multipliers Using FPGAs.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Gilberto Ochoa-Ruiz, Romain Bevan, Florent de Lamotte, Jean-Philippe Diguet, Cheng-Cong Bao	Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera	OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	David Wilson 0004, Aniruddha Shastri, Greg Stitt	A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid	Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing.	Int. J. Reconfig. Comp.	2017	DBLP DOI BibTeX RDF
1	Martin Kumm, Peter Zipf	Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs".	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Yee Hui Lee, Mohamed Khalil Hani, Muhammad Nadzir Marsono	An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Khalid Javeed, Xiaojun Wang	FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Jia Wei Tang, Nasir Shaikh-Husin, Usman Ullah Sheikh, Muhammad Nadzir Marsono	FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Amit Kulkarni 0002, Dirk Stroobandt	How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang	An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Chandrajit Pal, Avik Kotal, Asit Samanta, Amlan Chakrabarti, Ranjan Ghosh	An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Marcel Eckert, Dominik Meyer, Jan Haase, Bernd Klauer	Operating System Concepts for Reconfigurable Computing: Review and Survey.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Ahmed Al-Wattar, Shawki Areibi, Gary William Grewal	An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva	On-Chip Reconfigurable Hardware Accelerators for Popcount Computations.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Gaurav Purohit, Kota Solomon Raju, Vinod Kumar Chaubey	XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Anatolij Sergiyenko, Anastasia Serhienko	Modules for Pipelined Mixed Radix FFT Processors.	Int. J. Reconfig. Comp.	2016	DBLP DOI BibTeX RDF
1	Mahendra Vucha, Arvind Rajawat	Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Burhan Khurshid, Roohie Naaz Mir	High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Carlos A. Zerbini, Jorge M. Finochietto	Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono	Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Priya Gupta, Anu Gupta, Abhijit R. Asati	Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Tobias Kenter, Henning Schmitz, Christian Plessl	Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Fernando J. Barros	Representing Tactics for Fault Recovery: A Reconfigurable, Modular, and Hierarchical Approach.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Jonas Gomes Filho, Marius Strum, Jiang Chau Wang	Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Ali Asghar, Husain Parvez	An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Luis Andres Cardona, Carles Ferrer 0001	AC_ICAP: A Flexible High Speed ICAP Controller.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno	A Scalable Unsegmented Multiport Memory for FPGA-Based Systems.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George	Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs.	Int. J. Reconfig. Comp.	2015	DBLP DOI BibTeX RDF
1	Sharad Sinha, Thambipillai Srikanthan	Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Sharad Sinha, Thambipillai Srikanthan	IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Ariane Keller, Daniel Borkmann, Stephan Neuhaus, Markus Happe	Self-Awareness in Computer Networks.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Naveed Imran, Ronald F. DeMara	Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Mouna Ben Said, Yessine Hadj Kacem, Mickaël Kerboeuf, Nader Ben Amor, Mohamed Abid	Design Patterns for Self-Adaptive RTE Systems Specification.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang	FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Beau J. Tippetts, Dah-Jye Lee, Kirt D. Lillywhite, James K. Archibald	Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Senoj Joseph Olakkenghil, K. Baskaran	An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Spencer G. Fowers, Alok Desai, Dah-Jye Lee, Dan A. Ventura, James K. Archibald	TreeBASIS Feature Descriptor and Its Hardware Implementation.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Tim Todman, Stephan Stilkerich, Wayne Luk	Using Statistical Assertions to Guide Self-Adaptive Systems.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Leonid Moroz, Shinobu Nagayama, Taras Mykytiv, Ihor O. Kirenko, Taras Boretskyy	Simple Hybrid Scaling-Free CORDIC Solution for FPGAs.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Mouna Baklouti, Mohamed Abid	Multi-Softcore Architecture on FPGA.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Vanderlei Bonato, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo Marques	Practical Education Fostered by Research Projects in an Embedded Systems Course.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Guillermo A. Jaquenod, Javier Valls, Javier Siman	Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Mohsin Amin, Muhammad Shakir, Aqib Javed, Muhammad Hassan, Syed Ali Raza 0005	Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Alp Kiliç, Zied Marrakchi, Habib Mehrez	A Top-Down Optimization Methodology for Mutually Exclusive Applications.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Gayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani	Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration.	Int. J. Reconfig. Comp.	2014	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal	An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin	Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Zheming Jin, Jason D. Bakos	A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Malte Baesler, Sven-Ole Voigt	Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez	Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Taha Beyrouthy, Laurent Fesquet	An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi	Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill	Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Massimo Conti, Elmar U. K. Melcher, Jürgen Becker 0001, Alisson Vasconcelos De Brito, Oliver Sander	Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011).	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Emna Amouri, Habib Mehrez, Zied Marrakchi	Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada	Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Maitane Barrenechea, Mikel Mendicute, Egoitz Arruti	Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	René Cumplido, Peter Athanas, Jürgen Becker 0001	Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011).	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Gary William Grewal	Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Kais Loukil, Nader Ben Amor, Mohamed Abid, Jean-Philippe Diguet	Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira	Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid	Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform.	Int. J. Reconfig. Comp.	2013	DBLP DOI BibTeX RDF
1	Ali Akbar Zarezadeh, Christophe Bobda	Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich	Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Esam El-Araby, Iván González 0004, Sergio López-Buedo, Tarek A. El-Ghazawi	A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner	A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Christoph Starke 0001, Vasco Grossmann, Lars Wienbrandt, Sven Koschnicke, John Carstens, Manfred Schimmler	Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Diana Göhringer, Lukas Meder, Stephan Werner 0002, Oliver Oey, Jürgen Becker 0001, Michael Hübner	Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker 0001	Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Florent Bernard, Viktor Fischer, Crina Costea, Robert Fouquet	Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum	QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Zoltán Endre Rákossy, Zheng Wang 0020, Anupam Chattopadhyay	High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Zain-ul-Abdin, Bertil Svensson	Occam-pi for Programming of Massively Parallel Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF

Publications at "Int. J. Reconfig. Comp."( http://dblp.L3S.de/Venues/Int._J._Reconfig._Comp. )