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Publications at "Int. J. Reconfig. Comp."( http://dblp.L3S.de/Venues/Int._J._Reconfig._Comp. )

URL (DBLP): http://dblp.uni-trier.de/db/journals/ijrc

Publication years (Num. hits)
2008 (16) 2009 (35) 2010 (28) 2011 (40) 2012 (49) 2013 (17) 2014 (17) 2015-2016 (24) 2017-2018 (21) 2019 (9)
Publication types (Num. hits)
article(256)
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Found 256 publication records. Showing 256 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Nitish Das, P. Aruna Priya FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gianmarco Dinelli, Gabriele Meoni, Emilio Rapuano, Gionata Benelli, Luca Fanucci An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Michael Kirchhoff, Philipp Kerling, Detlef Streitferdt, Wolfgang Fengler 0001 A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Naveed Mahmud, Esam El-Araby Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Roberto Giorgi, Farnam Khalili, Marco Procaccini Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Karim M. A. Ali, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kizheppatt Vipin AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hamish J. Macintosh, Jasmine Banks, Neil A. Kelson Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ting Zhang, Bin Liu 0001 Exposing End-to-End Delay in Software-Defined Networking. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Faisal Mahmood, Mart Toots, Lars-Göran Öfverstedt, Ulf Skoglund Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ka Fai Cedric Yiu, Siow Yong Low On a Real-Time Blind Signal Separation Noise Reduction System. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Lilia Kechiche, Lamjed Touil, Bouraoui Ouni Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bruno da Silva, An Braeken, Federico Domínguez, Abdellah Touhafi Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Omar Ahmed, Shawki Areibi, Gary Gréwal Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm". Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly Corrigendum to "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability". Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization". Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei 0001, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, Huazhong Yang Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Qianqiao Chen, Vaibhawa Mishra, José Núñez-Yáñez, Georgios Zervas Reconfigurable Network Stream Processing on Virtualized FPGA Resources. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bahram N. Uchevler, Kjetil Svarstad Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin RP-Ring: A Heterogeneous Multi-FPGA Accelerator. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nitish Das, P. Aruna Priya FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Satheesh Bojja Venkatakrishnan, Elias A. Alwan, John L. Volakis Challenges in Clock Synchronization for On-Site Coding Digital Beamformer. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Aous H. Kurdi, Janos L. Grantner, Ikhlas Abdel-Qader Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini Efficient Realization of BCD Multipliers Using FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Gilberto Ochoa-Ruiz, Romain Bevan, Florent de Lamotte, Jean-Philippe Diguet, Cheng-Cong Bao Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1David Wilson 0004, Aniruddha Shastri, Greg Stitt A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Martin Kumm, Peter Zipf Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yee Hui Lee, Mohamed Khalil Hani, Muhammad Nadzir Marsono An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Khalid Javeed, Xiaojun Wang FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jia Wei Tang, Nasir Shaikh-Husin, Usman Ullah Sheikh, Muhammad Nadzir Marsono FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amit Kulkarni 0002, Dirk Stroobandt How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Chandrajit Pal, Avik Kotal, Asit Samanta, Amlan Chakrabarti, Ranjan Ghosh An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Marcel Eckert, Dominik Meyer, Jan Haase, Bernd Klauer Operating System Concepts for Reconfigurable Computing: Review and Survey. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ahmed Al-Wattar, Shawki Areibi, Gary William Grewal An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva On-Chip Reconfigurable Hardware Accelerators for Popcount Computations. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Gaurav Purohit, Kota Solomon Raju, Vinod Kumar Chaubey XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Anatolij Sergiyenko, Anastasia Serhienko Modules for Pipelined Mixed Radix FFT Processors. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mahendra Vucha, Arvind Rajawat Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Burhan Khurshid, Roohie Naaz Mir High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Carlos A. Zerbini, Jorge M. Finochietto Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Priya Gupta, Anu Gupta, Abhijit R. Asati Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Tobias Kenter, Henning Schmitz, Christian Plessl Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Fernando J. Barros Representing Tactics for Fault Recovery: A Reconfigurable, Modular, and Hierarchical Approach. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jonas Gomes Filho, Marius Strum, Jiang Chau Wang Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ali Asghar, Husain Parvez An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Luis Andres Cardona, Carles Ferrer 0001 AC_ICAP: A Flexible High Speed ICAP Controller. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Sharad Sinha, Thambipillai Srikanthan Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Sharad Sinha, Thambipillai Srikanthan IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Ariane Keller, Daniel Borkmann, Stephan Neuhaus, Markus Happe Self-Awareness in Computer Networks. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Naveed Imran, Ronald F. DeMara Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mouna Ben Said, Yessine Hadj Kacem, Mickaël Kerboeuf, Nader Ben Amor, Mohamed Abid Design Patterns for Self-Adaptive RTE Systems Specification. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Beau J. Tippetts, Dah-Jye Lee, Kirt D. Lillywhite, James K. Archibald Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Senoj Joseph Olakkenghil, K. Baskaran An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Spencer G. Fowers, Alok Desai, Dah-Jye Lee, Dan A. Ventura, James K. Archibald TreeBASIS Feature Descriptor and Its Hardware Implementation. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Tim Todman, Stephan Stilkerich, Wayne Luk Using Statistical Assertions to Guide Self-Adaptive Systems. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Leonid Moroz, Shinobu Nagayama, Taras Mykytiv, Ihor O. Kirenko, Taras Boretskyy Simple Hybrid Scaling-Free CORDIC Solution for FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mouna Baklouti, Mohamed Abid Multi-Softcore Architecture on FPGA. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Vanderlei Bonato, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo Marques Practical Education Fostered by Research Projects in an Embedded Systems Course. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Guillermo A. Jaquenod, Javier Valls, Javier Siman Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mohsin Amin, Muhammad Shakir, Aqib Javed, Muhammad Hassan, Syed Ali Raza 0005 Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Alp Kiliç, Zied Marrakchi, Habib Mehrez A Top-Down Optimization Methodology for Mutually Exclusive Applications. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Gayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Zheming Jin, Jason D. Bakos A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Malte Baesler, Sven-Ole Voigt Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Taha Beyrouthy, Laurent Fesquet An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Massimo Conti, Elmar U. K. Melcher, Jürgen Becker 0001, Alisson Vasconcelos De Brito, Oliver Sander Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011). Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Emna Amouri, Habib Mehrez, Zied Marrakchi Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Maitane Barrenechea, Mikel Mendicute, Egoitz Arruti Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1René Cumplido, Peter Athanas, Jürgen Becker 0001 Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Omar Ahmed, Shawki Areibi, Gary William Grewal Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kais Loukil, Nader Ben Amor, Mohamed Abid, Jean-Philippe Diguet Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ali Akbar Zarezadeh, Christophe Bobda Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Esam El-Araby, Iván González 0004, Sergio López-Buedo, Tarek A. El-Ghazawi A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Christoph Starke 0001, Vasco Grossmann, Lars Wienbrandt, Sven Koschnicke, John Carstens, Manfred Schimmler Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Kaveh Aasaraai, Andreas Moshovos NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Diana Göhringer, Lukas Meder, Stephan Werner 0002, Oliver Oey, Jürgen Becker 0001, Michael Hübner Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker 0001 Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Florent Bernard, Viktor Fischer, Crina Costea, Robert Fouquet Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Zoltán Endre Rákossy, Zheng Wang 0020, Anupam Chattopadhyay High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Zain-ul-Abdin, Bertil Svensson Occam-pi for Programming of Massively Parallel Reconfigurable Architectures. Search on Bibsonomy Int. J. Reconfig. Comp. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
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