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Publications of "Jürgen Teich" ( http://dblp.L3S.de/Authors/Jürgen_Teich )

URL (Homepage):  http://www12.informatik.uni-erlangen.de/people/teich/  Author page on DBLP  Author page in RDF  Community of Jürgen Teich in ASPL-2

Publication years (Num. hits)
1991-1998 (17) 1999-2001 (22) 2002-2003 (29) 2004 (20) 2005 (22) 2006 (30) 2007 (24) 2008 (40) 2009 (30) 2010 (37) 2011 (36) 2012 (33) 2013 (29) 2014 (49) 2015 (27) 2016 (32) 2017 (32) 2018 (29) 2019 (5)
Publication types (Num. hits)
article(112) book(5) incollection(11) inproceedings(406) phdthesis(1) proceedings(8)
Venues (Conferences, Journals, ...)
DATE(35) ASAP(21) FPL(21) ARCS(19) MBMV(19) DAC(16) CODES+ISSS(15) CoRR(15) FPT(15) FCCM(12) SCOPES(12) ReConFig(10) Dynamically Reconfigurable Arc...(8) FDL(8) IPDPS(8) ICSAMOS(7) More (+10 of total 168)
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The graphs summarize 99 occurrences of 76 keywords

Results
Found 544 publication records. Showing 543 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Search on Bibsonomy T. HiPEAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich Hard real-time application mapping reconfiguration for NoC-based many-core systems. Search on Bibsonomy Real-Time Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fedor Smirnov, Felix Reimann, Jürgen Teich, Michael Glaß Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2019 DBLP  BibTeX  RDF
1Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. Search on Bibsonomy BTW (Workshops) The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. Search on Bibsonomy CGO The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tulika Mitra, Jürgen Teich, Lothar Thiele Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II. Search on Bibsonomy IEEE Design & Test The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tulika Mitra, Jürgen Teich, Lothar Thiele Guest Editors' Introduction: Special Issue on Time-Critical Systems Design. Search on Bibsonomy IEEE Design & Test The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tulika Mitra, Jürgen Teich, Lothar Thiele Time-Critical Systems Design: A Survey. Search on Bibsonomy IEEE Design & Test The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Christian Schmitt 0003, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Search on Bibsonomy Parallel Processing Letters The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Christian Schmitt 0003, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer Automating the Development of High-Performance Multigrid Solvers. Search on Bibsonomy Proceedings of the IEEE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid Loop Parallelization Techniques for FPGA Accelerator Synthesis. Search on Bibsonomy Signal Processing Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. Search on Bibsonomy Embedded Systems Letters The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2018 DBLP  BibTeX  RDF
1Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Search on Bibsonomy Datenbank-Spektrum The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Faramarz Khosravi, Michael Borst, Jürgen Teich Probabilistic Dominance in Robust Multi-Objective Optimization. Search on Bibsonomy CEC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Daniel Ziener, Jutta Pirkl, Jürgen Teich Configuration Tampering of BRAM-based AES Implementations on FPGAs. Search on Bibsonomy ReConFig The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Franz-Josef Streit, Martin Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. Search on Bibsonomy ReConFig The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich Can Approximate Computing Reduce Power Consumption on FPGAs? Search on Bibsonomy ICECS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. Search on Bibsonomy DATE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß Architecture decomposition in system synthesis of heterogeneous many-core systems. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch Dynamic resource management for heterogeneous many-cores. Search on Bibsonomy ICCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jorge Echavarria, Stefan Wildermann, Jürgen Teich Design space exploration of multi-output logic function approximations. Search on Bibsonomy ICCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Michael Witterauf, Jürgen Teich Run-time Requirement Enforcement for Loop Programs on Processor Arrays. Search on Bibsonomy MEMOCODE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jonathan Ah Sue, Peter Brand, Johannes Brendel, Ralph Hasholzner, Joachim Falk, Jürgen Teich A predictive dynamic power management for LTE-Advanced mobile devices. Search on Bibsonomy WCNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. Search on Bibsonomy VEHITS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andreas Becher, Stefan Wildermann, Jürgen Teich Optimistic regular expression matching on FPGAs for near-data processing. Search on Bibsonomy DaMoN The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich On the Complexity of Mapping Feasibility in Many-Core Architectures. Search on Bibsonomy MCSoC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich Reinforcement Learning for Power-Efficient Grant Prediction in LTE. Search on Bibsonomy SCOPES The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich Automatic Kernel Fusion for Image Processing DSLs. Search on Bibsonomy SCOPES The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fedor Smirnov, Felix Reimann, Jürgen Teich, Zhao Han, Michael Glaß Automatic Optimization of Redundant Message Routings in Automotive Networks. Search on Bibsonomy SCOPES The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ericles Rodrigues Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. Search on Bibsonomy ASAP The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ayesha Afzal, Christian Schmitt 0003, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. Search on Bibsonomy ASAP The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hananeh Aliee, Emanuele Borgonovo, Michael Glaß, Jürgen Teich On the Boolean extension of the Birnbaum importance to non-coherent systems. Search on Bibsonomy Rel. Eng. & Sys. Safety The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Heba Khdr, Santiago Pagani, Ericles Rodrigues Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique 0001, Jürgen Teich, Jörg Henkel Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich Efficient task spawning for shared memory and message passing in many-core architectures. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zhenmin Li, HeeJong Park, Avinash Malik, Kevin I-Kai Wang, Zoran Salcic, Boris Kuzmin, Michael Glaß, Jürgen Teich Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Faramarz Khosravi, Michael Glaß, Jürgen Teich Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Search on Bibsonomy Integration The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. Search on Bibsonomy Signal Processing Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zoran Salcic, HeeJong Park, Jürgen Teich, Avinash Malik, Muhammad Nadeem Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Harald Köstler, Christian Schmitt 0003, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Search on Bibsonomy IJCSE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Birgit Vogel-Heuser, Stefan Wildermann, Jürgen Teich Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems. Search on Bibsonomy Production Engineering The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich Predictable run-time mapping reconfiguration for real-time applications on many-core systems. Search on Bibsonomy RTNS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ericles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. Search on Bibsonomy ReConFig The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ericles Rodrigues Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. Search on Bibsonomy ReConFig The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Behnaz Pourmohseni, Michael Glaß, Jürgen Teich Automatic operating point distillation for hybrid mapping methodologies. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Franz-Josef Streit, Martin Letras, Matthias Schid, Joachim Falk, Stefan Wildermann, Jürgen Teich High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. Search on Bibsonomy ICDSC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks. Search on Bibsonomy DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). Search on Bibsonomy ICCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hananeh Aliee, Abbas BanaiyanMofrad, Michael Glaß, Jürgen Teich, Nikil D. Dutt Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores. Search on Bibsonomy MBMV The full citation details ... 2017 DBLP  BibTeX  RDF
1Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. Search on Bibsonomy MCSoC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich Auto-vectorization for image processing DSLs. Search on Bibsonomy LCTES The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Martin Letras, Joachim Falk, Stefan Wildermann, Jürgen Teich Automatic Conversion of Simulink Models to SysteMoC Actor Networks. Search on Bibsonomy SCOPES The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. Search on Bibsonomy SCOPES The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jürgen Teich, Stefan Wildermann Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. Search on Bibsonomy SCOPES The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich Hardware design and analysis of efficient loop coarsening and border handling for image processing. Search on Bibsonomy ASAP The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich Efficiency in ILP processing by using orthogonality. Search on Bibsonomy ASAP The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa Convoy tracking for ADAS on embedded GPUs. Search on Bibsonomy Intelligent Vehicles Symposium The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Faramarz Khosravi, Hananeh Aliee, Jürgen Teich System-level reliability analysis considering imperfect fault coverage. Search on Bibsonomy ESTImedia The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sascha Roloff, Frank Hannig, Jürgen Teich High performance network-on-chip simulation by interval-based timing predictions. Search on Bibsonomy ESTImedia The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Michael Witterauf, Frank Hannig, Jürgen Teich Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. Search on Bibsonomy RSP The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber FPGA-Based Dynamically Reconfigurable SQL Query Processing. Search on Bibsonomy TRETS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Emanuele Borgonovo, Hananeh Aliee, Michael Glaß, Jürgen Teich A new time-independent reliability importance measure. Search on Bibsonomy European Journal of Operational Research The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Tulika Mitra, Jürgen Teich, Lothar Thiele Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). Search on Bibsonomy Dagstuhl Reports The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert HIPAcc: A Domain-Specific Language and Compiler for Image Processing. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Luca Fanucci, Jürgen Teich Recap of the 2016 DATE Conference & Exhibition. Search on Bibsonomy IEEE Design & Test The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yang Xu, Jürgen Teich Hierarchical Statistical Leakage Analysis and Its Application. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker Providing fault tolerance through invasive computing. Search on Bibsonomy it - Information Technology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau Invasive computing for timing-predictable stream processing on MPSoCs. Search on Bibsonomy it - Information Technology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jürgen Teich Invasive computing. Search on Bibsonomy it - Information Technology The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich HIPAcc. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jonathan Ah Sue, Ralph Hasholzner, Johannes Brendel, Martin Kleinsteuber, Jürgen Teich A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction. Search on Bibsonomy FAS*W@SASO/ICCAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Rafael Rosales, Christian Herglotz, Michael Glaß, André Kaup, Jürgen Teich Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling. Search on Bibsonomy ARCS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich (eds.) Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings Search on Bibsonomy ARCS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. Search on Bibsonomy ReConFig The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich ReOrder: Runtime datapath generation for high-throughput multi-stream processing. Search on Bibsonomy ReConFig The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hananeh Aliee, Stefan Vitzethum, Michael Glaß, Jürgen Teich, Emanuele Borgonovo Guiding Genetic Algorithms using importance measures for reliable design of embedded systems. Search on Bibsonomy DFT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich A LUT-Based Approximate Adder. Search on Bibsonomy FCCM The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Luca Fanucci, Jürgen Teich (eds.) 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016 Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Christian Herglotz, Rafael Rosales, Michael Glaß, Jürgen Teich, André Kaup Multi-objective design space exploration for the optimization of the HEVC mode decision process. Search on Bibsonomy PCS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich Formal reliability analysis of switched ethernet automotive networks under transient transmission errors. Search on Bibsonomy DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bo Wang 0010, Yang Xu, Ralph Hasholzner, Christian Drewes, Rafael Rosales, Sebastian Graf 0002, Joachim Falk, Michael Glaß, Jürgen Teich Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design. Search on Bibsonomy MBMV The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich FPGA-based accelerator design from a domain-specific language. Search on Bibsonomy FPL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. Search on Bibsonomy HLDVT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. Search on Bibsonomy FPT The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor. Search on Bibsonomy MCSoC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. Search on Bibsonomy MCSoC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich ActorX10: an actor library for X10. Search on Bibsonomy X10@PLDI The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. Search on Bibsonomy SCOPES The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. Search on Bibsonomy ASAP The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich A heterogeneous multi-core SoC for mixed criticality industrial automation systems. Search on Bibsonomy ETFA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich Hybrid code description for developing fast and resource efficient image processing architectures. Search on Bibsonomy SAMOS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Christian Schmitt 0003, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, Christian Lengauer Systems of Partial Differential Equations in ExaSlang. Search on Bibsonomy Software for Exascale Computing The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Ericles Rodrigues Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel Resource-awareness on heterogeneous MPSoCs for image processing. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer Techniques for on-demand structural redundancy for massively parallel processor arrays. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
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