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Publications of "Johann Knechtel" ( http://dblp.L3S.de/Authors/Johann_Knechtel )

  Author page on DBLP  Author page in RDF  Community of Johann Knechtel in ASPL-2

Publication years (Num. hits)
2011-2017 (16) 2018-2019 (24)
Publication types (Num. hits)
article(21) inproceedings(19)
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Found 41 publication records. Showing 40 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Abhrajit Sengupta, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Johann Knechtel, Jacek Gosciniak, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Mahmoud Rasras Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu Protect Your Chip Design Intellectual Property: An Overview. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu 3D Integration: Another Dimension Toward Hardware Security. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
1Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. Search on Bibsonomy IEEE Design & Test The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Search on Bibsonomy DATE The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu 3D Integration: Another Dimension Toward Hardware Security. Search on Bibsonomy IOLTS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu 0001, Evangeline F. Y. Young, Ozgur Sinanoglu Attacking Split Manufacturing from a Deep Learning Perspective. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu Protect Your Chip Design Intellectual Property: An Overview. Search on Bibsonomy COINS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Jens Lienig, Ibrahim Abe M. Elfadel Multi-Objective 3D Floorplanning with Integrated Voltage Assignment. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
1Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
1Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
1Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja Advancing hardware security using polymorphic and stochastic spin-hall effect devices. Search on Bibsonomy DATE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu Concerted wire lifting: Enabling secure and cost-effective split manufacturing. Search on Bibsonomy ASP-DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sergii Osmolovskyi, Johann Knechtel, Igor L. Markov, Jens Lienig Optimal die placement for interposer-based 3D ICs. Search on Bibsonomy ASP-DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. Search on Bibsonomy ICCAD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu Raise your game for split manufacturing: restoring the true functionality through BEOL. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. Search on Bibsonomy IPSJ Trans. System LSI Design Methodology The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Johann Knechtel, Ozgur Sinanoglu On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. Search on Bibsonomy ICCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. Search on Bibsonomy ICCAD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Ozgur Sinanoglu On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. Search on Bibsonomy DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Jens Lienig Physical Design Automation for 3D Chip Stacks: Challenges and Solutions. Search on Bibsonomy ISPD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Evangeline F. Y. Young, Jens Lienig Planning Massive Interconnects in 3-D Chips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Evangeline F. Y. Young, Jens Lienig Structural planning of 3D-IC interconnects by block alignment. Search on Bibsonomy ASP-DAC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Puskar Budhathoki, Johann Knechtel, Andreas Henschel, Ibrahim Abe M. Elfadel Integration of thermal management and floorplanning based on three-dimensional layout representations. Search on Bibsonomy ICECS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Robert Fischbach, Johann Knechtel, Jens Lienig Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. Search on Bibsonomy ISPD The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Igor L. Markov, Jens Lienig Assembling 2-D Blocks Into 3-D Chips. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Igor L. Markov, Jens Lienig, Matthias Thiele Multiobjective optimization of deadspace, a critical resource for 3D-IC integration. Search on Bibsonomy ICCAD The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Johann Knechtel, Igor L. Markov, Jens Lienig Assembling 2D blocks into 3D chips. Search on Bibsonomy ISPD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Robert Fischbach, Jens Lienig, Johann Knechtel Investigating modern layout representations for improved 3d design automation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
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