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Publications of Jose Flich José Flich Cardo ( http://dblp.L3S.de/Authors/Jose_Flich )

  Author page on DBLP  Author page in RDF  Community of José Flich in ASPL-2

Publication years (Num. hits)
1998-2002 (17) 2003-2004 (17) 2005-2006 (17) 2007-2008 (17) 2009-2011 (33) 2012-2013 (29) 2014-2015 (16) 2016-2019 (15)
Publication types (Num. hits)
article(47) incollection(2) inproceedings(111) proceedings(1)
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Found 162 publication records. Showing 161 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. Search on Bibsonomy JETC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tomás Picornell, José Flich, Carles Hernández, José Duato DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Miguel Gorgues Alonso, Jose Flich PROSA: Protocol-Driven Network on Chip Architecture. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. Search on Bibsonomy SAMOS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Edoardo Fusella, Jose Flich, Alessandro Cilardo Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. Search on Bibsonomy DSD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. Search on Bibsonomy PARCO The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1José V. Escamilla, Jose Flich, Mario R. Casu ICARO-PAPM: Congestion Management with Selective Queue Power-Gating. Search on Bibsonomy HPCS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Davide Zoni, Jose Flich, William Fornaciari CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Miguel Gorgues, Jose Flich End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein Logic-based implementation of fault-tolerant routing in 3D network-on-chips. Search on Bibsonomy NOCS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni Enabling HPC for QoS-sensitive applications: The MANGO approach. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1José V. Escamilla, Mario R. Casu, Jose Flich Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. Search on Bibsonomy MCSoC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Miguel Gorgues Alonso, José Flich Cardo PROSA: protocol-driven NoC architecture. Search on Bibsonomy NOCS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Search on Bibsonomy Design Autom. for Emb. Sys. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, Jose Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles 0001, José Duato Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, Mario Lodde, José Flich Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Search on Bibsonomy Computers & Electrical Engineering The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1André Ivanov, Diana Marculescu, Partha Pratim Pande, José Flich, Karthik Pattabiraman (eds.) Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015 Search on Bibsonomy NOCS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1José V. Escamilla, José Flich, Pedro Javier García Efficient DVFS Operation in NoCs Through a Proper Congestion Management Strategy. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni The MANGO FET-HPC Project: An Overview. Search on Bibsonomy CSE The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Alessandro Cilardo, Jose Flich, Mirko Gagliardi, Rafael Tornero Gavilá Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing. Search on Bibsonomy HPCC/CSS/ICESS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Marco Balboni, José Flich, Davide Bertozzi Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich d2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Edoardo Fusella, Jose Flich, Alessandro Cilardo, Antonino Mazzeo On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. Search on Bibsonomy SiPhotonics@HiPEAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1José Cano, Jose Flich, Antoni Roca 0001, José Duato, Marcello Coppola, Riccardo Locatelli Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Jose Flich, Hannu Tenhunen Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mario Lodde, José Flich Runtime home mapping for effective memory resource usage. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1José V. Escamilla, Jose Flich, Pedro Javier García ICARO: Congestion isolation in networks-on-chip. Search on Bibsonomy NOCS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Miguel Gorgues, Dong Xiang, Jose Flich, Zhigang Yu, José Duato Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm. Search on Bibsonomy NOCS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mario Lodde, Antoni Roca 0001, José Flich Built-in fast gather control network for efficient support of coherence protocols. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato Silicon-aware distributed switch architecture for on-chip networks. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001, Jose Flich, José Duato An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez 0002, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mario Lodde, Jose Flich An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance. Search on Bibsonomy NOCS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Davide Zoni, Jose Flich, William Fornaciari Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Bartosz Bogdanski, Bjørn Dag Johnsen, Sven-Arne Reinemo, José Flich Making the Network Scalable: Inter-subnet Routing in InfiniBand. Search on Bibsonomy Euro-Par The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1María Soler, José Flich Power Saving by NoC Traffic Compression. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mario Lodde, José Flich, Manuel E. Acacio Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Search on Bibsonomy Euro-Par The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mario Lodde, José Flich A Lightweight Network of IDs to Quickly Deliver Simple Control Messages. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Francisco Triviño, Davide Bertozzi, José Flich A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs. Search on Bibsonomy INA-OCMC@HiPEAC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Marco Balboni, Francisco Triviño, Jose Flich, Davide Bertozzi Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms. Search on Bibsonomy ISSoC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jose Flich, Scott Pakin, Craig B. Stunkel CASS Introduction. Search on Bibsonomy IPDPS Workshops The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1José V. Escamilla, Jose Flich, Pedro Javier García Head-of-Line Blocking Avoidance in Networks-on-Chip. Search on Bibsonomy IPDPS Workshops The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Tomohiro Yoneda, José Flich Cardo, Jiang Xu 0001, Michihiro Koibuchi Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). Search on Bibsonomy NII Shonan Meet. Rep. The full citation details ... 2013 DBLP  BibTeX  RDF
1José Flich Cardo, Maurizio Palesi Introduction to the special section on on-chip and off-chip network architectures. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1José Flich, Scott Pakin, Craig B. Stunkel Special issue on Communication Architectures for Scalable Systems. Search on Bibsonomy J. Parallel Distrib. Comput. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, José Flich Network-on-Chip virtualization in Chip-Multiprocessor Systems. Search on Bibsonomy Journal of Systems Architecture - Embedded Systems Design The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jose Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López 0001, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, Federico Silla, Jose Flich, José Duato On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Qiaoyan Yu, José Cano, José Flich, Paul Ampadu Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip. Search on Bibsonomy NOCS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mario Lodde, Jose Flich, Manuel E. Acacio Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. Search on Bibsonomy NOCS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato Enabling High-Performance Crossbars through a Floorplan-Aware Design. Search on Bibsonomy ICPP The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mario Lodde, Jose Flich, Manuel E. Acacio Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Search on Bibsonomy Euro-Par The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Albert Esteve, María Soler, María Engracia Gómez, Antonio Robles, José Flich Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Giorgos Dimitrakopoulos DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. Search on Bibsonomy FPL The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Francisco Triviño, José L. Sánchez 0002, Francisco José Alfaro, José Flich Exploring NoC Virtualization Alternatives in CMPs. Search on Bibsonomy PDP The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, Jose Flich OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. Search on Bibsonomy ICSAMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1José Flich, Scott Pakin, Craig B. Stunkel CASS Introduction. Search on Bibsonomy IPDPS Workshops The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, José Flich, Federico Silla, José Duato Characterizing the impact of process variation on 45 nm NoC-based CMPs. Search on Bibsonomy J. Parallel Distrib. Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001, José Flich, José Duato OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees. Search on Bibsonomy J. Parallel Distrib. Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001, José Flich, José Duato Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Search on Bibsonomy Concurrency and Computation: Practice and Experience The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Carles Hernández, Antoni Roca 0001, Jose Flich, Federico Silla, José Duato Fault-Tolerant Vertical Link Design for Effective 3D Stacking. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Rafael Tornero, Juan Manuel Orduña, Andres Mejia, Jose Flich, José Duato A Communication-Driven Routing Technique for Application-Specific NoCs. Search on Bibsonomy International Journal of Parallel Programming The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Francisco Triviño, José L. Sánchez 0002, Francisco José Alfaro, José Flich Virtualizing network-on-chip resources in chip-multiprocessors. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Federico Silla, José Duato A low-latency modular switch for CMP systems. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, José Flich, Antoni Roca 0001, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1José Flich Switch Architecture. Search on Bibsonomy Encyclopedia of Parallel Computing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1José Flich Flow Control. Search on Bibsonomy Encyclopedia of Parallel Computing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli Efficient routing implementation in complex systems-on-chip. Search on Bibsonomy NOCS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot Spidergon STNoC design flow. Search on Bibsonomy NOCS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, Jose Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles 0001, José Duato Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF HoL-blocking, Interconnection Networks, Congestion Management
1Antoni Roca 0001, Carles Hernández, José Flich, Federico Silla, José Duato A Distributed Switch Architecture for On-Chip Networks. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF switch implementation, network-on-chip
1Jesús Camacho Villanueva, José Flich, Antoni Roca 0001, José Duato PC-Mesh: A Dynamic Parallel Concentrated Mesh. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Francisco Triviño, Francisco José Alfaro, José L. Sánchez 0002, José Flich NoC Reconfiguration for CMP Virtualization. Search on Bibsonomy NCA The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski Towards an Efficient NoC Topology through Multiple Injection Ports. Search on Bibsonomy DSD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Camacho Villanueva, Jose Flich HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings. Search on Bibsonomy ANCS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF fault tolerance, topology, power consumption
1Francisco Triviño, Francisco José Alfaro, José L. Sánchez 0002, José Flich A fast centralized computation routing algorithm for self-configuring NoC systems. Search on Bibsonomy HiPC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1José Flich, Scott Pakin, Craig B. Stunkel CASS Introduction. Search on Bibsonomy IPDPS Workshops The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Teresa Nachiondo Frinós, Jose Flich, José Duato Buffer Management Strategies to Reduce HoL Blocking. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF distributed systems, network operating systems, computer systems organization, network architecture and design, Communication/networking and information technology
1Carles Hernández, Antoni Roca 0001, Federico Silla, Jose Flich, José Duato Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. Search on Bibsonomy NOCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, Jose Flich, Antoni Roca 0001, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. Search on Bibsonomy NOCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Fault-tolerance, Routing, Networks-on-chip
1José Flich, Alfonso Urso, Ulrich Brüning 0001, Giuseppe Di Fatta High Performance Networks. Search on Bibsonomy Euro-Par (2) The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, Jose Flich, Federico Silla, José Duato A Latency-Efficient Router Architecture for CMP Systems. Search on Bibsonomy DSD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001, José Flich, José Duato Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. Search on Bibsonomy ICPADS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Antoni Roca 0001, José Flich, Federico Silla, José Duato VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. Search on Bibsonomy HiPC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Scott Pakin, Craig B. Stunkel, Jose Flich, Henrique Andrade, Vibhore Kumar, Deepak S. Turaga Welcome to CAC/SSPS 2010. Search on Bibsonomy IPDPS Workshops The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López 0001, Rickard Holsmark, José Duato Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato Efficient implementation of distributed routing algorithms for NoCs. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez 0002, Jose Flich, Francisco J. Quiles 0001, José Duato A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, Wladek Olesinski A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors. Search on Bibsonomy NoCArc@MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Vicente Chirivella, Rosa Alcover, Jose Flich, José Duato Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy. Search on Bibsonomy Euro-Par The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Olav Lysne, José Miguel Montañana, Jose Flich, José Duato, Timothy Mark Pinkston, Tor Skeie An Efficient and Deadlock-Free Network Reconfiguration Protocol. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Interconnections (Subsystems), Topology, I/O and Data Communications
1José Flich, José Duato Logic-Based Distributed Routing for NoCs. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne On the Potential of NoC Virtualization for Multicore Chips. Search on Bibsonomy Scalable Computing: Practice and Experience The full citation details ... 2008 DBLP  BibTeX  RDF
1Hans Eberle, Pedro Javier García, Jose Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins, Wladek Olesinski High-radix crossbar switches enabled by proximity communication. Search on Bibsonomy SC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jose Flich, Samuel Rodrigo, José Duato An Efficient Implementation of Distributed Routing Algorithms for NoCs. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF routing implementation, router architecture
1Andres Mejia, Jose Flich, José Duato On the Potentials of Segment-Based Routing for NoCs. Search on Bibsonomy ICPP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Samuel Rodrigo, Jose Flich, José Duato, Mark Hummel Efficient unicast and multicast support for CMPs. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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