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Publications of "Josef Strnadel" ( http://dblp.L3S.de/Authors/Josef_Strnadel )

  Author page on DBLP  Author page in RDF  Community of Josef Strnadel in ASPL-2

Publication years (Num. hits)
2002-2010 (16) 2011-2018 (12)
Publication types (Num. hits)
article(4) inproceedings(24)
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Found 29 publication records. Showing 28 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Josef Strnadel Predictability Analysis of Interruptible Systems by Statistical Model Checking. Search on Bibsonomy IEEE Design & Test The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. Search on Bibsonomy ISoLA (2) The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Josef Strnadel On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. Search on Bibsonomy DSD The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Josef Strnadel On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. Search on Bibsonomy ISoLA (1) The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. Search on Bibsonomy ECBS-EERC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Frantisek Slimarik Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Search on Bibsonomy Computing and Informatics The full citation details ... 2014 DBLP  BibTeX  RDF
1Josef Strnadel, Martin Pokorny Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. Search on Bibsonomy DSD The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. Search on Bibsonomy ARCS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Josef Strnadel On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. Search on Bibsonomy DDECS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Frantisek Slimarik On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. Search on Bibsonomy DSD The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. Search on Bibsonomy DDECS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Michal Rumplík, Josef Strnadel On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. Search on Bibsonomy DSD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. Search on Bibsonomy DSD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel Reduction of power dissipation through parallel optimization of test vector and scan register sequences. Search on Bibsonomy DDECS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. Search on Bibsonomy ICES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Tomas Pecenka, Zdenek Kotásek Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Search on Bibsonomy Computing and Informatics The full citation details ... 2008 DBLP  BibTeX  RDF
1Josef Strnadel TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Richard Ruzicka, Josef Strnadel Test Controller Synthesis Constrained by Circuit Testability Analysis. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Search on Bibsonomy Computers and Artificial Intelligence The full citation details ... 2006 DBLP  BibTeX  RDF
1Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina Testability Estimation Based on Controllability and Observability Parameters. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Josef Strnadel Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. Search on Bibsonomy DDECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Arghya Kumar Dhali Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. Search on Bibsonomy ECBS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Zdenek Kotásek SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. Search on Bibsonomy ECBS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Zdenek Kotásek Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Search on Bibsonomy Evolvable Hardware The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Daniel Mika, Josef Strnadel, Zdenek Kotásek The Identification of registers in RTL Structures for the Test Application. Search on Bibsonomy ISoLA (Preliminary proceedings) The full citation details ... 2004 DBLP  BibTeX  RDF
1Zdenek Kotásek, Daniel Mika, Josef Strnadel Test scheduling for embedded systems. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Josef Strnadel, Zdenek Kotásek Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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