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Publications of "Kuen-Jong Lee" ( http://dblp.L3S.de/Authors/Kuen-Jong_Lee )

  Author page on DBLP  Author page in RDF  Community of Kuen-Jong Lee in ASPL-2

Publication years (Num. hits)
1990-1997 (15) 1998-2001 (18) 2002-2006 (15) 2007-2011 (19) 2012-2014 (16) 2015-2017 (16) 2018-2019 (7)
Publication types (Num. hits)
article(36) inproceedings(70)
Venues (Conferences, Journals, ...)
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The graphs summarize 61 occurrences of 47 keywords

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Found 107 publication records. Showing 106 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Chao-Jun Shang, Cheng-Hung Wu, Kuen-Jong Lee, Yu-Hsiang Chen A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model. Search on Bibsonomy VLSI-DAT The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy A Repair-for-Diagnosis Methodology for Logic Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Chun-Wei Wu, Kuen-Jong Lee, Alan P. Su A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Chia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks. Search on Bibsonomy ATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. Search on Bibsonomy ITC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jhen-Zong Chen, Kuen-Jong Lee Test Stimulus Compression Based on Broadcast Scan With One Single Input. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee Test Compression with Single-Input Data Spreader and Multiple Test Sessions. Search on Bibsonomy ATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hsin-Pang Kuo, Alan P. Su, Kuen-Jong Lee A low power synthesis flow for multi-rate systems. Search on Bibsonomy VLSI-DAT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shuo-Lian Hong, Kuen-Jong Lee A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. Search on Bibsonomy ITC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. Search on Bibsonomy ASP-DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. Search on Bibsonomy ASP-DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. Search on Bibsonomy ATS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich Autonomous Testing for 3D-ICs with IEEE Std. 1687. Search on Bibsonomy ATS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte An on-chip self-test architecture with test patterns recorded in scan chains. Search on Bibsonomy ITC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Kuen-Jong Lee Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. Search on Bibsonomy ITC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee Output bit selection methodology for test response compaction. Search on Bibsonomy ITC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. Search on Bibsonomy ASP-DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee Distinguishing dynamic bridging faults and transition delay faults. Search on Bibsonomy ASICON The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee Improve transition fault diagnosability via observation point insertion. Search on Bibsonomy VLSI-DAT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Chin-Yao Chang, Kuen-Jong Lee On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty Efficient LFSR Reseeding Based on Internal-Response Feedback. Search on Bibsonomy J. Electronic Testing The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh Output-bit selection with X-avoidance using multiple counters for test-response compaction. Search on Bibsonomy ETS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Kuen-Jong Lee An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. Search on Bibsonomy ATS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. Search on Bibsonomy VTS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh Output selection for test response compaction based on multiple counters. Search on Bibsonomy VLSI-DAT The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Cheng-Hung Wu An efficient diagnosis-aware pattern generation procedure for transition faults. Search on Bibsonomy ITC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu Counter-Based Output Selection for Test Response Compaction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty A New LFSR Reseeding Scheme via Internal Response Feedback. Search on Bibsonomy Asian Test Symposium The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip. Search on Bibsonomy VLSI-DAT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Search on Bibsonomy Asian Test Symposium The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty Accumulator-based output selection for test response compaction. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee Routing-efficient implementation of an internal-response-based BIST architecture. Search on Bibsonomy VLSI-DAT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Chin-Long Wey Programmable System-on-Chip for Silicon Prototyping. Search on Bibsonomy IEEE Trans. Industrial Electronics The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh Test Response Compaction via Output Bit Selection. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Chin-Yao Chang, I-Jou Chen EPIDETOX: an ESL platform for integrated circuit design and tool exploration. Search on Bibsonomy CODES+ISSS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu A software/hardware co-debug platform for multi-core systems. Search on Bibsonomy ASICON The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Wei-Cheng Lien, Kuen-Jong Lee A Complete Logic BIST Technology with No Storage Requirement. Search on Bibsonomy Asian Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li Turbo1500: Core-Based Design for Test and Diagnosis. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao Full System Simulation and Verification Framework. Search on Bibsonomy IAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. Search on Bibsonomy Asian Test Symposium The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su A low-cost SOC debug platform based on on-chip test architectures. Search on Bibsonomy SoCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee Tolerance of performance degrading faults for effective yield improvement. Search on Bibsonomy ITC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer An Error Rate Based Test Methodology to Support Error-Tolerance. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee A hybrid software-based self-testing methodology for embedded processor. Search on Bibsonomy SAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF embedded processor testing, fault coverage, functional testing, software-based self-test
1Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen A Software-Based Test Methodology for Direct-Mapped Data Cache. Search on Bibsonomy ATS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee A hybrid self-testing methodology of processor cores. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. Search on Bibsonomy ITC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer Reduction of detected acceptable faults for yield improvement via error-tolerance. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. Search on Bibsonomy SoCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee A high speed BIST architecture for DDR-SDRAM testing. Search on Bibsonomy MTDT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Wei-Lun Wang, Kuen-Jong Lee A complete memory address generator for scan based March algorithms. Search on Bibsonomy MTDT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong An embedded processor based SOC test platform. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer A novel test methodology based on error-rate to support error-tolerance. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho Test Power Reduction with Multiple Capture Orders. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee Test pattern generation and clock disabling for simultaneous test time and power reduction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee An efficient BIST method for distributed small buffers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Tsung-Chu Huang An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. Search on Bibsonomy J. Electronic Testing The full citation details ... 2002 DBLP  DOI  BibTeX  RDF multiple scan chains, interleaving scan, test power reduction, peak power reduction
1Wei-Lun Wang, Kuen-Jong Lee An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. Search on Bibsonomy J. Electronic Testing The full citation details ... 2002 DBLP  DOI  BibTeX  RDF mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain
1Kuen-Jong Lee, Chau-chin Su Guest Editorial. Search on Bibsonomy J. Electronic Testing The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Jih-Jeen Chen Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang An on-chip march pattern generator for testing embedded memory cores. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Tsung-Chu Huang, Kuen-Jong Lee Reduction of power consumption in scan-based circuits during testapplication by an input control technique. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Yun-Che Wen, Kuen-Jong Lee Analysis and generation of control and observation structures foranalog circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Tsung-Chu Huang, Kuen-Jong Lee A Low-Power LFSR Architecture. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Tsung-Chu Huang, Kuen-Jong Lee A token scan architecture for low power testing. Search on Bibsonomy ITC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Yun-Che Wen, Kuen-Jong Lee An on Chip ADC Test Structure. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Wei-Lun Wang, Kuen-Jong Lee Accelerated test pattern generators for mixed-mode BIST environments. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
1Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen Peak-power reduction for multiple-scan circuits during test application. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
1Kuen-Jong Lee, Cheng-I Huang A hierarchical test control architecture for core based design. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
1Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang Broadcasting test patterns to multiple circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Tsung-Chu Huang, Kuen-Jong Lee An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
1Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee An Efficient BIST Method for Small Buffers. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang A General Structure of Feedback Shift Registers for Built-In Self Test. Search on Bibsonomy J. Inf. Sci. Eng. The full citation details ... 1998 DBLP  BibTeX  RDF
1Kuen-Jong Lee, Cheng-Hsuing Kuo Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. Search on Bibsonomy J. Inf. Sci. Eng. The full citation details ... 1998 DBLP  BibTeX  RDF
1Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu A graph representation for programmable logic arrays to facilitate testing and logic design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang Using a single input to support multiple scan chains. Search on Bibsonomy ICCAD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF boundary scan (IEEE 1149.1) and test compaction, test generation, design for testability, scan based design
1Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee Built-in current sensor designs based on the bulk-driven technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF bulk-driven current mirror, biasing schemes, low power dissipation, power supply voltage drop, circuit speed degradation, external power supply, 0.3 V, 0.3 ns, accuracy, flexibility, simplicity, built-in current sensor, area overhead, I/sub DDQ/ testing, electric current measurement
1Kuen-Jong Lee, Jing-Jou Tang Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
1Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
1Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu A practical current sensing technique for IDDQ testing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer An integrated system for assigning signal flow directions to CMOS transistors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu Built-in intermediate voltage testing for CMOS circuits. Search on Bibsonomy ED&TC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee A New Architecture for Analog Boundary Scan. Search on Bibsonomy ISCAS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). Search on Bibsonomy ISCAS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer SWiTEST: a switch level test generation system for CMOS combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
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