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Publications at "LATS"( http://dblp.L3S.de/Venues/LATS )

URL (DBLP): http://dblp.uni-trier.de/db/conf/latw

Publication years (Num. hits)
2015 (50) 2016 (44) 2017 (36) 2018 (46) 2019 (40)
Publication types (Num. hits)
inproceedings(211) proceedings(5)
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LATS(216)
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Found 216 publication records. Showing 216 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Enrique Alvarez-Fontecilla, Angel Abusleme A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs). Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fabio Benevenuti, Fernanda Lima Kastensmidt Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Thiago Santos Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Vazquez, Juan Luis Castagnola, Fortunato Carlos Dualibe OBT applied to a 2nd order continuous time Feedforward Sigma Delta modulator. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cezar A. Rigo, Lucas M. Luza, Elder Dominghini Tramontin, Victor M. Goncalves Martins, Sara Vega Martinez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo A. Bezerra A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Salem Abdennadher, Arani Sinha, Yonghyun Kim Analog/Mixed Signal IP DFx from a Foundry perspective. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1 IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019 Search on Bibsonomy LATS The full citation details ... 2019 DBLP  BibTeX  RDF
1Ayman A. Atallah, Ghaith Bany Hamad, Otmane Aït Mohamed Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez Softerror mitigation for multi-core processors based on thread replication. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Estevan Lara, Guilherme Debon, Roger C. Goerl, Paulo Ricardo Cechelero Villa, Dorian Schramm, Leticia B. Poehls, Fabian Vargas A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luiz G. S. Dias, Carlos J. Gonzalez, Fernando J. Boeira, Tiago R. Balen Electromagnetic Immunity Test of Analog-to-Digital Interfaces of a Mixed-Signal Programmable SoC. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Raphael Segabinazzi Ferreira, Jörg Nolte Low latency reconfiguration mechanism for fine-grained processor internal functional units. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rodrigo Zeli, Reinaldo Silveira, Qadeer Qureshi SoC Memory Test Optimization using NXP MTR Solutions. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alberto Bosio, Paolo Bernardi, Annachiara Ruospo, Ernesto Sánchez 0001 A Reliability Analysis of a Deep Neural Network. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1I. D. Meza-Ibarra, Víctor H. Champac, R. Gómez-Fuentes, J. R. Noriega, A. Vera-Marquina Identification of Logic Paths Influenced by Severe Coupling Capacitances. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Matheus Monteiro Mariano, Érica Ferreira de Souza, André Takeshi Endo, Nandamudi L. Vijaykumar Analyzing graph-based algorithms employed to generate test cases from finite state machines. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alexander Aponte-Moreno, Felipe Restrepo-Calle, César Pedraza MiFIT: A Fault Injection Tool to Validate the Reliability of Microprocessors. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik Mixed-level identification of fault redundancy in microprocessors. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Alexander Aponte-Moreno, César Pedraza, Felipe Restrepo-Calle Reducing Overheads in Software-based Fault Tolerant Systems using Approximate Computing. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui Software-Based Mitigation for Memory Address Decoder Aging. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko Qubit-driven Fault Simulation. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Martin Krcma, Zdenek Kotásek, Jakub Lojda Detecting hard synapses faults in artificial neural networks. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Juan M. Alvarez Q., John A. Sanabria O., Jose I Garcia M. Microservices-based architecture for fault diagnosis in tele-rehabilitation equipment operated via Internet. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Karel Szurman, Zdenek Kotásek Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens Defect-Location Identification for Cell-Aware Test. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daniel Sánchez, Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Dardo Vinas Viscardi A Wireless Embedded System for Measuring the Effects of Ionizing Radiations. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abhishek Das, Nur A. Touba Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Lorena Anghel, Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Ioana I. Vatajelu Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1H. El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre Use of ensemble methods for indirect test of RF circuits: can it bring benefits? Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone On the evaluation of SEU effects in GPGPUs. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Daniel Sánchez, Dardo Vinas Viscardi Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Roberto Gómez, Víctor H. Champac A metric-guided gate-sizing methodology for aging guardband reduction. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Rodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas, Eduardo Augusto Bezerra Processor core profiling for SEU effect analysis. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fábio B. Armelin, Lírida A. B. Naviner, Roberto d'Amore Using FPGA self-produced transients to emulate SETs for SER estimation. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alexander Aponte-Moreno, Alejandro Moncada, Felipe Restrepo-Calle, César Pedraza A review of approximate computing techniques towards fault mitigation in HW/SW systems. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jerrin Pathrose, Ghazanfar Ali, Hans G. Kerkhoff IJTAG compatible analogue embedded instruments for MPSoC life-time prediction. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Paulo Vinicius Cardoso, Patricia Pitthan Barcelos Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Carlos L. G. Batista, Eliane Martins, Maria de Fátima Mattiello-Francisco On the use of a failure emulator mechanism at nanosatellite subsystems integration tests. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hassen Aziza, Karine Coulié, Wenceslas Rahajandraibe, Remy Vauche Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim Direct optimization of a PCI express link equalization in industrial post-silicon validation. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui, Marco Rovatti Ionizing radiation modeling in DRAM transistors. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Juliano Oliveira, Marcilei Aparecida Guazzelli, Marco Antonio Assis, Renato Giacomini Single event effect: Simulations and analysis on 3N163 PMOS transistor. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Marcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio Testing approximate digital circuits: Challenges and opportunities. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andrea Marcelli, Ernesto Sánchez 0001, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, Davide Pola, Alessandro Salvato, Michele Simili Defeating hardware Trojan in microprocessor cores through software obfuscation. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dionisio de Carvalho, Bruno Sanches, M. De Carvalho, Wilhelmus A. M. Van Noije A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fabio Benevenuti, Fernanda Lima Kastensmidt Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1 19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018 Search on Bibsonomy LATS The full citation details ... 2018 DBLP  BibTeX  RDF
1Augusto Einsfeldt, Renato Giacomini Fault-tolerant architecture with full recovery under presence of SEU. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Marcos Silveira Santos, Roberto d'Amore Error detection method for the ARINC429 communication. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas, Eduardo Augusto Bezerra Processor checkpoint recovery for transient faults in critical applications. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Gabriel Natan P. Silva, Ricardo O. Duarte Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen Fault masking ratio analysis of majority voters topologies. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Joao de Moraes, Taisy Weber, Guilherme Muller, Tiago Dall'Agnol, Rafael Macedo, Elaine P. L. Scartezzini, Roque E. Dapper, Sérgio Cechin, Joao Netto Architecture of an industrial analog input designed to meet safety requirements. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Rafael Melo Macieira, Edna Barros TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Vazquez, Tinus Stander, Fortunato C. Dualibe Influence of passive oscillator component variation on OBT sensitivity in OTAs. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fábio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore Probability aware fault-injection approach for SER estimation. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Renato Severo, Celso Maciel da Costa, Adriane Parraga, Debora Motta, Ivan Müller, Fabian Vargas Design and test of the RT-NKE task scheduling algorithm for multicore architectures. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Eduardo Garcia-Espinosa, Omar Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero Post-silicon validation based on synthetic test patterns for early detection of timing anomalies. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Felix Mühlbauer, Lukas Schröder, Mario Schölzel A fault tolerant dynamically scheduled processor with partial permanent fault handling. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alexandra Kourfali, Dirk Stroobandt Superimposed in-circuit debugging for self-healing FPGA overlays. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Luiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Israel C. Lopes, Fabio Benevenuti, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Paolo Rech Reliability analysis on case-study traffic sign convolutional neural network on APSoC. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez 0001, Matteo Sonza Reorda About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Stefano Esposito, Jacopo Sini, Massimo Violante Real-time validation of mixed-criticality applications. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Salem Abdennadher, Michael Altmann, Bin Xue Challenges and emerging solutions in testing HBM IO & systems. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1George Redivo Pinto, Guilherme Cardoso Medeiros, Fabian Vargas, Leticia Bolzani Poehls A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Thales E. Becker, Fábio Fedrizzi Vidor, Gilson I. Wirth, Thorsten Meyers, Julia Reker, Ulrich Hilleringmann Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module). Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Stefano Esposito, Serhiy Avramenko, Massimo Violante RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Lucas M. V. Pereira, Douglas R. Melo, Cesar Albenes Zeferino, Eduardo A. Bezerra Analysis of LEON3 systems integration for a Network-on-Chip. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Reinaldo Silveira, Qadeer Qureshi, Rodrigo Zeli Flexible architecture of memory BISTs. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt Improving approximate-TMR using multi-objective optimization genetic algorithm. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker 0001 Evaluating the effectiveness of D-chains in SAT-based ATPG. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Oscar Acevedo Patino, Juan Carlos Martínez Santos Physical-aware pattern selection for stuck-at faults. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ronaldo Milfont, Paulo Cortez 0002, Alan Cadore Pinheiro, Joao Marcelo Ferreira, Jarbas Silveira, Rafael Mota, César A. M. Marcon Analysis of routing algorithms generation for irregular NoC topologies. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Paulo Ricardo Cechelero Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina, Nemitala Added, Vitor A. P. de Aguiar, Eduardo L. A. Macchione, Fernando Aguirre, Marcilei A. G. da Silveira, Eduardo Augusto Bezerra Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac Analysis of short defects in FinFET based logic cells. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre Contrast of a HDL model and COTS version of a microprocessor for soft-error testing. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Felix Mühlbauer, Lukas Schröder, Patryk Skoncej, Mario Schölzel Handling manufacturing and aging faults with software-based techniques in tiny embedded systems. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Oscar Acevedo, Dimitri Kagaris LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generation. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt Fault injection methodology for single event effects on clock-gated ASICs. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1G. An, Riccardo Cantoro, Ernesto Sánchez 0001, Matteo Sonza Reorda On the detection of board delay faults through the execution of functional programs. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Israel C. Lopes, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Carlos J. Gonzalez, Cristiano P. Chenet, Matheus Budelon, Rafael Galhardo Vaz, Odair Lelis Goncalez, Tiago R. Balen Evaluation of a mixed-signal design diversity system under radiation effects. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
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