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Publications of "Leibo Liu" ( http://dblp.L3S.de/Authors/Leibo_Liu )

URL (Homepage):  https://orcid.org/0000-0001-7548-4116  Author page on DBLP  Author page in RDF  Community of Leibo Liu in ASPL-2

Publication years (Num. hits)
2002-2010 (18) 2011-2013 (32) 2014 (20) 2015 (42) 2016 (21) 2017 (24) 2018 (28) 2019 (24)
Publication types (Num. hits)
article(116) book(1) inproceedings(92)
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Found 210 publication records. Showing 209 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han 0001 An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han 0001 Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie 0001, Shaojun Wei Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Qiang Wang, Wenping Zhu, Huiyu Mo, Tianchen Wang, Shouyi Yin, Yiyu Shi, Shaojun Wei A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei Reconfigurable Architecture for Neural Approximation in Multimedia Computing. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Liang Wang, Ping Lv, Leibo Liu, Jie Han 0001, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Huiyu Mo, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei Face Alignment With Expression- and Pose-Based Adaptive Initialization. Search on Bibsonomy IEEE Trans. Multimedia The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Man Shi, Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Leibo Liu, Pieter P. Jonker, Duncan G. Elliott, Fabrizio Lombardi, Jie Han 0001 A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Guiqiang Peng, Shaojun Wei Massive MIMO Detection Algorithm and VLSI Architecture Search on Bibsonomy 2019   DOI  RDF
1Leibo Liu, Ao Luo, Guanhua Li, Jianfeng Zhu, Yong Wang, Gang Shan, Jianfeng Pan, Shouyi Yin, Shaojun Wei Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. Search on Bibsonomy Hot Chips Symposium The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang 0006, Jie Han 0001, Leibo Liu, Weisheng Zhao Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. Search on Bibsonomy ISVLSI The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei Constructing Concurrent Data Structures on FPGA with Channels. Search on Bibsonomy FPGA The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Zhaoshi Li, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, Shaojun Wei FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. Search on Bibsonomy MICRO The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao 0003, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. Search on Bibsonomy ISCAS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han 0001 Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xingchen Man, Leibo Liu, Jianfeng Zhu, Shaojun Wei A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Wenjing Hu, Yao Wang, Shaojun Wei A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hong Liu, Leibo Liu, Wenping Zhu, Qiang Li, Huiyu Mo, Shaojun Wei L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Shaojun Wei Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. Search on Bibsonomy IEEE Access The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Peican Zhu, Xiaogang Song, Leibo Liu, Zhen Wang, Jie Han 0001 Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation. Search on Bibsonomy IEEE Access The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi, Shaojun Wei Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jiale Yan, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Bo Wang 0023, Chenchen Deng, Min Zhu 0001, Shouyi Yin, Shaojun Wei Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Chen Yang 0005, Shouyi Yin, Shaojun Wei CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu 0001, Shouyi Yin, Shengyang Mao DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Siting Liu, Honglan Jiang, Leibo Liu, Jie Han 0001 Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei FP-BNN: Binarized neural network on FPGA. Search on Bibsonomy Neurocomputing The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Guiqiang Peng, Leibo Liu, Sheng Zhou, Yang Xue, Shouyi Yin, Shaojun Wei Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems. Search on Bibsonomy IEEE Trans. Signal Processing The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Peng Ouyang, Shouyi Yin, Leibo Liu, Youguang Zhang, Weisheng Zhao, Shaojun Wei A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Zhaoshi Li, Chen Yang 0005, Chenchen Deng, Shouyi Yin, Shaojun Wei HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han 0001 Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. Search on Bibsonomy DATE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei Bit-width Adaptive Accelerator Design for Convolution Neural Network. Search on Bibsonomy ISCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. Search on Bibsonomy ISCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Guiqiang Peng, Leibo Liu, Qiushi Wei, Yao Wang, Shouyi Yin, Shaojun Wei A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. Search on Bibsonomy A-SSCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. Search on Bibsonomy ISCA The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hang Yuan, Leibo Liu, Hui Li, Shouyi Yin, Shaojun Wei A Full Multicast Reconfigurable Non-blocking Permutation Network. Search on Bibsonomy CyberC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Yingjie Chen, Chenchen Deng, Shouyi Yin, Shaojun Wei Implementation of in-loop filter for HEVC decoder on reconfigurable processor. Search on Bibsonomy IET Image Processing The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Weizhi Xu, Shouyi Yin, Zhen Zhang, Hao Dong, Rui Shi, Leibo Liu, Shaojun Wei Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. Search on Bibsonomy IEEE Access The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chen Yang 0005, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chen Wu, Chenchen Deng, Leibo Liu, Jie Han 0001, Jiqiang Chen, Shouyi Yin, Shaojun Wei A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Xu Dai, Leibo Liu, Shaojun Wei An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. Search on Bibsonomy IEEE Systems Journal The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Cong Liu 0015, Leibo Liu, Fabrizio Lombardi, Jie Han 0001 A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits. Search on Bibsonomy JETC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Guiqiang Peng, Leibo Liu, Peng Zhang, Shouyi Yin, Shaojun Wei Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. Search on Bibsonomy IEEE Trans. Signal Processing The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Bo Wang 0023, Leibo Liu, Chenchen Deng, Min Zhu 0001, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. Search on Bibsonomy IEEE Trans. Information Forensics and Security The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chenchen Deng, Leibo Liu, Yang Liu, Shouyi Yin, Shaojun Wei PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu, Shaojun Wei Multi-CNN and decision tree based driving behavior evaluation. Search on Bibsonomy SAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, JinZhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. Search on Bibsonomy NVMSA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. Search on Bibsonomy ASP-DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Honglan Jiang, Leibo Liu, Jie Han 0001 An efficient hardware design for cerebellar models using approximate circuits: special session paper. Search on Bibsonomy CODES+ISSS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. Search on Bibsonomy FCCM The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei Memory fartitioning-based modulo scheduling for high-level synthesis. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu, Shaojun Wei DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. Search on Bibsonomy ISCA The full citation details ... 2017 DBLP  BibTeX  RDF
1Qiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment. Search on Bibsonomy DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution. Search on Bibsonomy DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. Search on Bibsonomy Computer Architecture Letters The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Peican Zhu, Jie Han 0001, Leibo Liu, Fabrizio Lombardi Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu, Shaojun Wei CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei Trigger-Centric Loop Mapping on CGRAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Dong Wang, Yingjie Chen, Min Zhu 0001, Shouyi Yin, Shaojun Wei An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. Search on Bibsonomy IEICE Transactions The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Leibo Liu, Junbin Wang, Jianfeng Zhu, Chenchen Deng, Shouyi Yin, Shaojun Wei TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Wenping Zhu, Leibo Liu, Guangli Jiang, Shouyi Yin, Shaojun Wei A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bo Wang 0023, Leibo Liu Dynamically reconfigurable architecture for symmetric ciphers. Search on Bibsonomy SCIENCE CHINA Information Sciences The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Peng Ouyang, Shouyi Yin, Chenchen Deng, Leibo Liu, Shaojun Wei A fast face detection architecture for auto-focus in smart-phones and digital cameras. Search on Bibsonomy SCIENCE CHINA Information Sciences The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bo Wang 0023, Leibo Liu, Chenchen Deng, Min Zhu 0001, Shouyi Yin, Shaojun Wei Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. Search on Bibsonomy IEEE Trans. Information Forensics and Security The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. Search on Bibsonomy ASP-DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei Multibank memory optimization for parallel data access in multiple data arrays. Search on Bibsonomy ICCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. Search on Bibsonomy ICCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei Energy management on DVS based coarse-grained reconfigurable platform. Search on Bibsonomy NANOARCH The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Chen Yang 0005, Leibo Liu, Shouyi Yin, Shaojun Wei Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. Search on Bibsonomy DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Yu Ren, Leibo Liu, Shouyi Yin, Jie Han 0001, Shaojun Wei Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. Search on Bibsonomy TRETS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Peican Zhu, Jie Han 0001, Leibo Liu, Fabrizio Lombardi A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jianfeng Zhu, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
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