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Publications of "Mahesh Mehendale" ( http://dblp.L3S.de/Authors/Mahesh_Mehendale )

  Author page on DBLP  Author page in RDF  Community of Mahesh Mehendale in ASPL-2

Publication years (Num. hits)
1989-1998 (20) 1999-2011 (16) 2012-2018 (14)
Publication types (Num. hits)
article(3) inproceedings(47)
Venues (Conferences, Journals, ...)
VLSI Design(21) ISSCC(5) ICCAD(4) DAC(3) ASP-DAC(2) EURO-DAC(1) ICASSP(1) ICCE(1) ICPE(1) ICS(1) IEEE Trans. Circuits Syst. Vid...(1) IEEE Trans. VLSI Syst.(1) ISCAS(1) ISCAS (3)(1) ISLPED(1) MEMSYS(1) More (+10 of total 20)
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The graphs summarize 32 occurrences of 26 keywords

Results
Found 51 publication records. Showing 50 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Manikandan R. R., Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam Session 14 overview: Deep-learning processors. Search on Bibsonomy ISSCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nagendra Gulur, R. Govindarajan, Mahesh Mehendale MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. Search on Bibsonomy MEMSYS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Luke Shin Session 4 overview: Digital processors. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata F1: Designing secure systems: Manufacturing, circuits and architectures. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale 8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. Search on Bibsonomy ISSCC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Dipan Kumar Mandal, Mihir Mody, Mahesh Mehendale, Naresh Yadav, Ghone Chaitanya, Piyali Goswami, Hetul Sanghvi, Niraj Nandan Accelerating H.264/HEVC video slice processing using application specific instruction set processor. Search on Bibsonomy ICCE The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan A Comprehensive Analytical Performance Model of DRAM Caches. Search on Bibsonomy ICPE The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan ANATOMY: an analytical model of memory system performance. Search on Bibsonomy SIGMETRICS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. Search on Bibsonomy MICRO The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry A 28nm programmable and low power ultra-HD video codec engine. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry A monolithic programmable Ultra-HD video codec engine. Search on Bibsonomy ICASSP The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. Search on Bibsonomy ICS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. Search on Bibsonomy PACT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Subash G. Chandar, Mahesh Mehendale, R. Govindarajan Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF embedded DSP systems, re-configurable architecture, code compression, energy reduction
1Mahesh Mehendale SoC - The Road Ahead. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale Challenges in the Design of Embedded Real-time DSP SoCs. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei Emerging markets: design goes global. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Amitabh Menon, S. K. Nandy, Mahesh Mehendale Multivoltage scheduling with voltage-partitioned variable storage. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multivoltage, high level synthesis, datapath synthesis
1Mahesh Mehendale, Santhosh Kumar Amanna Functional Verification of Programmable DSP Cores. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair Performance Considerations in Embedded DSP based System-On-a-Chip Designs. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Vikas Agrawal, Anand Pande, Mahesh Mehendale High Level Synthesis Of Multi-Precision Data Flow Graphs. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Subash G. Chandar, Mahesh Mehendale, R. Govindarajan Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. Search on Bibsonomy ICCAD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1M. N. Mahesh, Mahesh Mehendale Low Power Realization of Residue Number System Based FIR Filters. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Low power implementation, DSP, Residue Number System(RNS), FIR filters
1Mahesh Mehendale, Sunil D. Sherlekar Power Reduction Techniques for Portable DSP Applications. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Sunil D. Sherlekar Low Power Code Generation of Multiplication-free Linear Transforms. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1M. N. Mahesh, Mahesh Mehendale Improving performance of high precision signal processing algorithms on programmable DSPs. Search on Bibsonomy ISCAS (3) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Low-power realization of FIR filters on programmable DSPs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
1Amit Sinha, Mahesh Mehendale mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF FIR Filters, Distributed Arithmetic, Area Estimation
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Hardware/Software High Level Synthesis, Low Power Design, FIR Filters
1Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF High Level Synthesis-Transformations, FIR Filters
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Extensions to Programmable DSP architectures for Reduced Power Dissipation. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Low Power Design, DSP Architecture
1Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. Search on Bibsonomy ASP-DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Low power realization of FIR filters using multirate architectures. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
1Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar Optimized Code Generation of Multiplication-free Linear Transforms. Search on Bibsonomy DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, M. K. Ram Prasad AATMA: an algorithm for technology mapping for antifuse-based FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF AATMA, antifuse-based FPGAs, logic module structure, complex functions, signature-matching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Techniques for low power realization for FIR filters. Search on Bibsonomy ASP-DAC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh Synthesis of multiplier-less FIR filters with minimum number of additions. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF MCM based structures, iterative elimination, low pass FIR filters, circuit CAD, FIR filters, network synthesis, optimizing transformations, binary representations
1Mahesh Mehendale, Biswadip Mitra An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. Search on Bibsonomy VLSI Design The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, Kaushik Roy 0001 Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. Search on Bibsonomy VLSI Design The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. Search on Bibsonomy DAC The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. Search on Bibsonomy VLSI Design The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale, P. Murugavel, M. Poornima SLIM: A System for ASIC Library Management. Search on Bibsonomy ICCAD The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
1Mahesh Mehendale An approach to design flow management in CAD frameworks. Search on Bibsonomy EURO-DAC The full citation details ... 1991 DBLP  BibTeX  RDF
1Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild FDT-a design tool for switched capacitor filters. Search on Bibsonomy ICCAD The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
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