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Publications of "Marc Renaudin" ( http://dblp.L3S.de/Authors/Marc_Renaudin )

  Author page on DBLP  Author page in RDF  Community of Marc Renaudin in ASPL-2

Publication years (Num. hits)
1993-2002 (17) 2003-2005 (28) 2006-2007 (27) 2008-2010 (16) 2011-2018 (10)
Publication types (Num. hits)
article(19) inproceedings(79)
Venues (Conferences, Journals, ...)
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The graphs summarize 37 occurrences of 36 keywords

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Found 99 publication records. Showing 98 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. Search on Bibsonomy J. Low Power Electronics The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin Adaptive rate filtering a computationally efficient signal processing approach. Search on Bibsonomy Signal Processing The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels Clockless Design Performance Monitoring for Nanometer Technologies. Search on Bibsonomy ASYNC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Alex Yakovlev, Pascal Vivet, Marc Renaudin Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. Search on Bibsonomy DATE The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. Search on Bibsonomy ASYNC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Alain Fonkoua Tiempo Asynchronous Circuits System Verilog Modeling Language. Search on Bibsonomy ASYNC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. Search on Bibsonomy J. Cryptology The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback Search on Bibsonomy CoRR The full citation details ... 2011 DBLP  BibTeX  RDF
1Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Search on Bibsonomy Microelectronics Reliability The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Marc Renaudin ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. Search on Bibsonomy PATMOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis Evaluating transient-fault effects on traditional C-element's implementations. Search on Bibsonomy IOLTS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. Search on Bibsonomy European Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. Search on Bibsonomy ASAP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin Constrained Asynchronous Ring Structures for Robust Digital Oscillators. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. Search on Bibsonomy EURASIP J. Adv. Sig. Proc. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. Search on Bibsonomy VTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis Comparing transient-fault effects on synchronous and on asynchronous circuits. Search on Bibsonomy IOLTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin Programmable/Stoppable Oscillator Based on Self-Timed Rings. Search on Bibsonomy ASYNC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. Search on Bibsonomy J. Electrical and Computer Engineering The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin Physical Design of FPGA Interconnect to Prevent Information Leakage. Search on Bibsonomy ARC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Eslam Yahya, Marc Renaudin Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. Search on Bibsonomy ICECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. Search on Bibsonomy IOLTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. Search on Bibsonomy ASYNC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon Parallel Asynchronous Watershed Algorithm-Architecture. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Asynchronous algorithm-architecture, performance evaluation, image segmentation, hill-climbing, correctness proof, parallel processors, watershed
1N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin FPGA Architecture for Multi-Style Asynchronous Logic Search on Bibsonomy CoRR The full citation details ... 2007 DBLP  BibTeX  RDF
1G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain DPA on quasi delay insensitive asynchronous circuits: formalization and improvement Search on Bibsonomy CoRR The full citation details ... 2007 DBLP  BibTeX  RDF
1J. Fragoso, Gilles Sicard, Marc Renaudin Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Search on Bibsonomy Technique et Science Informatiques The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Sylvain Miermont, Pascal Vivet, Marc Renaudin A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Cedric Koch-Hofer, Marc Renaudin Timed Asynchronous Circuits Modeling using SystemC. Search on Bibsonomy FDL The full citation details ... 2007 DBLP  BibTeX  RDF
1Julien Goulier, Eric André, Marc Renaudin A new analytical approach of the impact of jitter on continuous time delta sigma converters. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Julien Goulier, Eric André, Marc Renaudin A new analytical approach of the impact of jitter on continuous time delta sigma converters. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Eslam Yahya, Marc Renaudin Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. Search on Bibsonomy ICECS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Yannick Monnet, Marc Renaudin, Régis Leveugle Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst A Novel Asynchronous e-FPGA Architecture for Security Applications. Search on Bibsonomy FPT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. Search on Bibsonomy ICASSP (3) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin Computationally efficient adaptive rate sampling and filtering. Search on Bibsonomy EUSIPCO The full citation details ... 2007 DBLP  BibTeX  RDF
1Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. Search on Bibsonomy SECON The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. Search on Bibsonomy J. Low Power Electronics The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Yannick Monnet, Marc Renaudin, Régis Leveugle Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
1Eslam Yahya, Marc Renaudin QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin State-holding in Look-Up Tables: application to asynchronous logic. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin Security evaluation of dual rail logic against DPA attacks. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. Search on Bibsonomy FDTC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Estelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger A 100dB dynamic range CMOS image sensor with global shutter. Search on Bibsonomy ICECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF QDI Asynchronous circuits, Path Swapping (PS), Power analysis
1Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. Search on Bibsonomy IOLTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Yannick Monnet Asynchronous Design: Fault Robustness and Security Characteristics. Search on Bibsonomy IOLTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin Spectral analysis of a signal driven sampling scheme. Search on Bibsonomy EUSIPCO The full citation details ... 2006 DBLP  BibTeX  RDF
1Laurent Fesquet, Jerome Quartana, Marc Renaudin Asynchronous Systems on Programmable Logic. Search on Bibsonomy ReCoSoC The full citation details ... 2005 DBLP  BibTeX  RDF
1Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine A Method to Design Compact Dual-rail Asynchronous Primitives. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1David Rios-Arambula, Aurélien Buhrig, Marc Renaudin Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Jerome Quartana, Laurent Fesquet, Marc Renaudin Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. Search on Bibsonomy VLSI-SoC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. Search on Bibsonomy VLSI-SoC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. Search on Bibsonomy VLSI-SoC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Aurélien Buhrig, Marc Renaudin, Dominique Barthel Asynchrnous Architecture for Sensor Network Nodes. Search on Bibsonomy Med-Hoc-Net The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin FPGA Architecture for Multi-Style Asynchronous Logic. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Yannick Monnet, Marc Renaudin, Régis Leveugle Asynchronous circuits transient faults sensitivity evaluation. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
1Yannick Monnet, Marc Renaudin, Régis Leveugle Hardening Techniques against Transient Faults for Asynchronous Circuits. Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. Search on Bibsonomy FPL The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Laurent Fesquet, Marc Renaudin A Programmable Logic Architecture for Prototyping Clockless Circuits. Search on Bibsonomy FPL The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin A 120nm low power asynchronous ADC. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF asynchronous technology, level-crossing sampling, analog-to-digital conversion
1Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Search on Bibsonomy Annales des Télécommunications The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Dhanistha Panyasak, Gilles Sicard, Marc Renaudin A current shaping methodology for lowering em disturbances in asynchronous circuits. Search on Bibsonomy Microelectronics Journal The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin TAST Profiler and Low Energy Asynchronous Design Methodology. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain High Security Smartcards. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Yannick Monnet, Marc Renaudin, Régis Leveugle Asynchronous Circuits Sensitivity to Fault Injection. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin Asynchronous FIR Filters: Towards a New Digital Processing Chain. Search on Bibsonomy ASYNC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Level-crossing sampling, FIR filter, Speech processing, Asynchronous design, Irregular sampling
1João Leonardo Fragoso, Gilles Sicard, Marc Renaudin Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin Statistic Implementation of QDI Asynchronous Primitives. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani Validation of asynchronous circuit specifications using IF/CADP. Search on Bibsonomy VLSI-SOC The full citation details ... 2003 DBLP  BibTeX  RDF
1Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani Validation of Asynchronous Circuit Specifications Using IF/CADP. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin A New Class of Asynchronous A/D Converters Based on Time Quantization. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1João Leonardo Fragoso, Gilles Sicard, Marc Renaudin Automatic Generation of 1-of-M QDI Asynchronous Adders. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. Search on Bibsonomy HICSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard Low-Power Asynchronous A/D Conversion. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin Dynamic Voltage Scheduling for Real Time Asynchronous Systems. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland Implementing Asynchronous Circuits on LUT Based FPGAs. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon Watershed parallel algorithm for asynchronous processors array. Search on Bibsonomy ICME (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. Search on Bibsonomy IWLS The full citation details ... 2002 DBLP  BibTeX  RDF
1Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés Low-power systems on chips (SOCs). Search on Bibsonomy DATE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. Search on Bibsonomy VLSI-SOC The full citation details ... 2001 DBLP  BibTeX  RDF
1Marc Renaudin, Pascal Vivet, Frédéric Robin A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Pascal Vivet, Frédéric Robin ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
1Frédéric Robin, Gilles Privat, Marc Renaudin Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. Search on Bibsonomy IJPRAI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
1Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering Self timed division and square-root extraction. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks
1Hicham Boutamine, Alain Guyot, Bachar El Hassan, Marc Renaudin Asynchronous SRT Dividers: The Real Cost. Search on Bibsonomy ED&TC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. Search on Bibsonomy ISCAS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Marc Renaudin, Bachar El Hassan The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. Search on Bibsonomy ISCAS The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1A. K. Betts, Ivo Bolsens, E. Sicard, Marc Renaudin, A. Johnstone SMILE: A scalable microcontroller library element. Search on Bibsonomy Microprocessing and Microprogramming The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
1Michel Poize, Marc Renaudin, Patrick Venier A general time domain approach for the design of perfect reconstruction modulated filter banks. Search on Bibsonomy ICASSP (3) The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
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