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Publications of "Masanori Furuta" ( http://dblp.L3S.de/Authors/Masanori_Furuta )

  Author page on DBLP  Author page in RDF  Community of Masanori Furuta in ASPL-2

Publication years (Num. hits)
2003-2013 (16) 2014-2019 (12)
Publication types (Num. hits)
article(12) inproceedings(16)
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Found 29 publication records. Showing 28 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Adam B. Cellon, Adebayo A. Eisape, Masanori Furuta, Ralph Etienne-Cummings Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware. Search on Bibsonomy ISCAS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura 28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. Search on Bibsonomy ISSCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. Search on Bibsonomy IEICE Transactions The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura 6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura 19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura 26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. Search on Bibsonomy ISCAS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. Search on Bibsonomy IEICE Transactions The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. Search on Bibsonomy ISCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. Search on Bibsonomy IEICE Transactions The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. Search on Bibsonomy VLSI-DAT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Mai Nozawa, Tetsuro Itakura A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. Search on Bibsonomy A-SSCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Mai Nozawa, Tetsuro Itakura A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura An area-efficient sampling rate converter using negative feedback technique. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Kazutaka Honda, Masanori Furuta, Shoji Kawahito A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters. Search on Bibsonomy IEEE Trans. Instrumentation and Measurement The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits. Search on Bibsonomy CICC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Zheng Liu, Masanori Furuta, Shoji Kawahito Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits. Search on Bibsonomy IEICE Transactions The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Kazutaka Honda, Masanori Furuta, Shoji Kawahito A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Shoji Kawahito, Kazutaka Honda, Masanori Furuta, Nobuhiro Kawai, Daisuke Miyazaki Low-Power Design of High-Speed A/D Converters. Search on Bibsonomy IEICE Transactions The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta A digitally skew correctable multi-phase clock generator using a master-slave DLL. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
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