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Publications of "Michel Renovell" ( http://dblp.L3S.de/Authors/Michel_Renovell )

  Author page on DBLP  Author page in RDF  Community of Michel Renovell in ASPL-2

Publication years (Num. hits)
1985-1996 (16) 1997-1998 (17) 1999-2001 (26) 2002-2004 (26) 2005-2006 (17) 2007-2009 (15) 2010-2014 (22) 2015-2017 (15) 2018-2019 (6)
Publication types (Num. hits)
article(55) inproceedings(102) proceedings(3)
Venues (Conferences, Journals, ...)
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The graphs summarize 167 occurrences of 82 keywords

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Found 161 publication records. Showing 160 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac Modeling and Detectability of Full Open Gate Defects in FinFET Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. Search on Bibsonomy J. Electronic Testing The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Michel Renovell, Víctor H. Champac B-open: A New Defect in Nanometer Technologies due to SADP Process. Search on Bibsonomy ETS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. Search on Bibsonomy J. Electronic Testing The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. Search on Bibsonomy J. Electronic Testing The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. Search on Bibsonomy ISVLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras Mitigating read & write errors in STT-MRAM memories under DVS. Search on Bibsonomy ETS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Amit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. Search on Bibsonomy ETS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac Analysis of short defects in FinFET based logic cells. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Michel Renovell Spot defect modeling: Past and evolution. Search on Bibsonomy DTIS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Michel Renovell, Víctor H. Champac Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. Search on Bibsonomy ISVLSI The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac Behavior and test of open-gate defects in FinFET based cells. Search on Bibsonomy ETS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. Search on Bibsonomy LATS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Search on Bibsonomy Microelectronics Journal The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. Search on Bibsonomy ISVLSI The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. Search on Bibsonomy ISVLSI The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras Power-aware voltage tuning for STT-MRAM reliability. Search on Bibsonomy ETS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements. Search on Bibsonomy Microelectronics Journal The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Elena I. Vatajelu, Alvaro Gómez-Pau, Michel Renovell, Joan Figueras Sram cell stability metric under transient voltage noise. Search on Bibsonomy Microelectronics Journal The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Serge Bernard, Patrick Garda, Michel Renovell Editorial. Search on Bibsonomy Microelectronics Journal The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jean Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell Testing for gate oxide short defects using the detectability interval paradigm. Search on Bibsonomy it - Information Technology The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell New implementions of predictive alternate analog/RF test with augmented model redundancy. Search on Bibsonomy DATE The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos Solutions for the self-adaptation of communicating systems in operation. Search on Bibsonomy IOLTS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. Search on Bibsonomy LATW The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Ioannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale DTIS 2014 foreword. Search on Bibsonomy DTIS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Search on Bibsonomy Microelectronics Journal The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell Implementing model redundancy in predictive alternate test to improve test confidence. Search on Bibsonomy ETS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1J. Jiang, M. Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. Search on Bibsonomy Asian Test Symposium The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzerho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti Accurate and efficient analytical electrical model of antenna for NFC applications. Search on Bibsonomy NEWCAS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1M. Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, J. Jiang, Ilia Polian, Bernd Becker 0001 Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. Search on Bibsonomy LATW The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Víctor H. Champac, Michel Renovell Low voltage testing for interconnect opens under process variations. Search on Bibsonomy LATW The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma Smart selection of indirect parameters for DC-based alternate RF IC testing. Search on Bibsonomy VTS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell Making predictive analog/RF alternate test strategy independent of training set size. Search on Bibsonomy ITC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. Search on Bibsonomy J. Electronic Testing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell Influence of parasitic memory effect on single-cell faults in SRAMs. Search on Bibsonomy DDECS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Elena I. Vatajelu, Alvaro Gómez-Pau, Michel Renovell, Joan Figueras Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Search on Bibsonomy Asian Test Symposium The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Víctor H. Champac, Michel Renovell A new methodology for realistic open defect detection probability evaluation under process variations. Search on Bibsonomy VTS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Mohamed Masmoudi, Michel Renovell Editorial. Search on Bibsonomy Microelectronics Journal The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Sandra Irobi, Zaid Al-Ars, Michel Renovell Parasitic memory effect in CMOS SRAMs. Search on Bibsonomy IDT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1M. Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell Functional Testing of Processor Cores in FPGA-Based Applications. Search on Bibsonomy Computing and Informatics The full citation details ... 2009 DBLP  BibTeX  RDF
1Piet Engelke, Bernd Becker 0001, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation
1Florence Azaïs, Yves Bertrand, Michel Renovell An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker 0001 An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Search on Bibsonomy VTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker 0001 On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová (eds.) Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008 Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  BibTeX  RDF
1Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker 0001 A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Search on Bibsonomy European Test Symposium The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Small-delay defects, resistive opens, probabilistic fault coverage, bridging fault simulation
1Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta 0001 (eds.) Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008 Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  BibTeX  RDF
1Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. Search on Bibsonomy IOLTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. Search on Bibsonomy J. Electronic Testing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Analog built-in self-test, Transient response analysis, FPAA
1Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Philippe Cauvet, Serge Bernard, Michel Renovell System-in-Package, a Combination of Challenges and Solutions. Search on Bibsonomy European Test Symposium The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. Search on Bibsonomy European Test Symposium The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Simulating Resistive-Bridging and Stuck-At Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Automatic Test Pattern Generation for Resistive Bridging Faults. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF resistive short defects, ATPG, SAT, bridging faults
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF BIST, delay faults, look-up table
1Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF DFT, ADC, mixed-signal testing, SiP, DAC, system-in-package
1Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell Functional Test of Field Programmable Analog Arrays. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF analog built-in self-test, transient response analysis, FPAA
1Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell Electrical Behavior of GOS Fault affected Domino Logic Cell. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Gate-Oxide Short (GOS), Electrical analysis Boolean test, Domino logic, Defect modeling
1Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand Delay Testing Viability of Gate Oxide Short Defects. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF gate oxide short (GOS), VLSI, delay testing, defect
1Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001 Modeling Feedback Bridging Faults with Non-Zero Resistance. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF feedback bridging faults, resistive bridging faults, bridging fault simulation
1Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPAA test, Oscillation Test Strategy (OTS), Built-In Self Test (BIST), analog testing
1Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF testability evaluation, design-for-test, analog and mixed-signal testing
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF look-up table (LUT), FPGA, test, delay fault
1Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF test, spectral analysis, ADC
1Adoración Rueda, Michel Renovell, José Luis Huertas Guest Editorial. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell Built-in self-test of global interconnects of field programmable analog arrays. Search on Bibsonomy Microelectronics Journal The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker 0001 Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Deep submicron technology modeling, Resistive bridging faults
1Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
1Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell A New FPGA for DSP Applications Integrating BIST Capabilities. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF hardware test, FPGA, digital signal processing, DSP, BIST, reconfigurable architectures
1Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF test flow optimization, analog and mixed-signal testing, ADC test
1Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF spectral analysis, analog and mixed-signal testing, ADC test
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. Search on Bibsonomy European Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Automatic test pattern generation for resistive bridging faults. Search on Bibsonomy European Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs Analysis and Attenuation Proposal in Ground Bounce. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell Scan Design and Secure Chip. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker 0001 The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Very-Low-Voltage testing, Resistive short defects
1Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Michel Renovell Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. Search on Bibsonomy Journal of Circuits, Systems, and Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF minimal-length transistors, fault modeling, gate oxide short
1Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell A-to-D converters static error detection from dynamic parameter measurement. Search on Bibsonomy Microelectronics Journal The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand Delay Testing of MOS Transistor with Gate Oxide Short. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell Defect Analysis for Delay-Fault BIST in FPGAs. Search on Bibsonomy IOLTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Simulating Resistive Bridging and Stuck-At Faults. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
1Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell A New Methodology For ADC Test Flow Optimization. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Michel Renovell, Florence Azaïs, Yves Bertrand Improving Defect Detection in Static-Voltage Testing. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Manfred Glesner, Peter Zipf, Michel Renovell (eds.) Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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