The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Publications of "Mohammed Benaissa" ( http://dblp.L3S.de/Authors/Mohammed_Benaissa )

  Author page on DBLP  Author page in RDF  Community of Mohammed Benaissa in ASPL-2

Publication years (Num. hits)
1993-2003 (16) 2004-2008 (21) 2009-2012 (17) 2013-2018 (17) 2019 (1)
Publication types (Num. hits)
article(26) incollection(1) inproceedings(45)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 32 occurrences of 27 keywords

Results
Found 73 publication records. Showing 72 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ahmed Al-Baidhani, Mikko Vehkaperä, Mohammed Benaissa Simultaneous Wireless Information and Power Transfer Based on Generalized Triangular Decomposition. Search on Bibsonomy TGCN The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sarmad Al-gawwam, Mohammed Benaissa Robust Eye Blink Detection Based on Eye Landmarks and Savitzky-Golay Filtering. Search on Bibsonomy Information The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Krishna Chaitanya Patchava, Mohammed Benaissa, Hatim Behairy, Saleh AlShebeili Improved Support Vector Regression Coupled with Fourier Self-Deconvolution in the Quantitative Analysis of Glucose in NIR Spectra. Search on Bibsonomy IISA The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ahmed Al-Baidhani, Mohammed Benaissa, Mikko Vehkaperä Wireless Information and Power Transfer Based on Generalized Triangular Decomposition. Search on Bibsonomy GLOBECOM The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sarmad Al-gawwam, Mohammed Benaissa Depression Detection From Eye Blink Features. Search on Bibsonomy ISSPIT The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ahmed Al-Baidhani, Mohammed Benaissa, Mikko Vehkaperä Transceiver Design for Data Rate Maximization of MIMO SWIPT System Based on Generalized Triangular Decomposition. Search on Bibsonomy WCSP The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shakirah Hashim, Mohammed Benaissa Accelerating Integer Based Fully Homomorphic Encryption Using Frequency Domain Multiplication. Search on Bibsonomy ICICS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Zia Uddin Ahamed Khan, Mohammed Benaissa High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Osamah Abdulhameed Alrezj, Krishna Chaitanya Patchava, Mohammed Benaissa, Saleh AlShebeili Coupling Scatter Correction with bandpass filtering for preprocessing in the quantitative analysis of glucose from near infrared spectra. Search on Bibsonomy EMBC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Krishna Chaitanya Patchava, Osamah Alrezj, Mohammed Benaissa, Hatim Behairy Savitzky-golay coupled with digital bandpass filtering as a pre-processing technique in the quantitative analysis of glucose from near infrared spectra. Search on Bibsonomy EMBC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1M. S. Albahri, Mohammed Benaissa, Zia Uddin Ahamed Khan Parallel Implementation of ECC Point Multiplication on a Homogeneous Multi-Core Microcontroller. Search on Bibsonomy MSN The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zia Uddin Ahamed Khan, Mohammed Benaissa Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Krishna Chaitanya Patchava, Mohammed Benaissa, Hatim Behairy Improving the prediction performance of PLSR using RReliefF and FSD for the quantitative analysis of glucose in Near Infrared spectra. Search on Bibsonomy EMBC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Zia Uddin Ahamed Khan, Mohammed Benaissa High speed ECC implementation on FPGA over GF(2m). Search on Bibsonomy FPL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1M. S. Albahri, Mohammed Benaissa Parallel comba multiplication in GF(2163) using homogenous multicore microcontroller. Search on Bibsonomy ICECS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa A holistic approach examining RFID design for security and privacy. Search on Bibsonomy The Journal of Supercomputing The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Junfeng Chu, Mohammed Benaissa Error detecting AES using polynomial residue number systems. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Zia Uddin Ahamed Khan, Mohammed Benaissa Low area ECC implementation on FPGA. Search on Bibsonomy ICECS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Anastasios Kanakis, Bilal Malik, Mohammed Benaissa Low Cost Universal Remote Patient Monitoring System. Search on Bibsonomy HPCC-ICESS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Bilal Malik, Mohammed Benaissa Determination of glucose concentration from near-infrared spectra using locally weighted partial least square regression. Search on Bibsonomy EMBC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mohammed Benaissa, Bilal Malik, Anastasios Kanakis, N. P. Wright Tele-healthcare for diabetes management: A low cost automatic approach. Search on Bibsonomy EMBC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Junfeng Chu, Mohammed Benaissa Low area memory-free FPGA implementation of the AES algorithm. Search on Bibsonomy FPL The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Junfeng Chu, Mohammed Benaissa A Novel Architecture of Implementing Error Detecting AES Using PRNS. Search on Bibsonomy DSD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa 692-nW Advanced Encryption Standard (AES) on a 0.13-mum CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Omar Nibouche, Said Boussakta, Michael Darnell, Mohammed Benaissa Algorithms and pipeline architectures for 2-D FFT and FFT-like transforms. Search on Bibsonomy Digital Signal Processing The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa Efficient Time-Area Scalable ECC Processor Using µ-Coding Technique. Search on Bibsonomy WAIFI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa Small Footprint Implementations of Scalable ECC Point Multiplication on FPGA. Search on Bibsonomy ICC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Saleh Suleman Saraireh, Mohammed Benaissa A scalable block cipher design using filter banks over finite fields. Search on Bibsonomy ICASSP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa A scalable hardware/software co-design for elliptic curve cryptography on PicoBlaze microcontroller. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa, Anastasios Kanakis Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications. Search on Bibsonomy ASAP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa Embedded Software Design of Scalable Low-Area Elliptic-Curve Cryptography. Search on Bibsonomy Embedded Systems Letters The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Saleh Suleman Saraireh, Mohammed Benaissa A Scalable Block Cipher Design Using Filter Banks and Lifting over Finite Fields. Search on Bibsonomy ICC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Mohammed Benaissa, Tim Good A Low-Frequency RFID to Challenge Security and Privacy Concerns. Search on Bibsonomy MASS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa Low Area-Scalable Hardware/Software Co-Design for Elliptic Curve Cryptography. Search on Bibsonomy NTMS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Junfeng Chu, Mohammed Benaissa Polynomial Residue Number System GF(2m) multiplier using trinomials. Search on Bibsonomy EUSIPCO The full citation details ... 2009 DBLP  BibTeX  RDF
1William N. Chelton, Mohammed Benaissa Fast Elliptic Curve Cryptography on FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1William N. Chelton, Mohammed Benaissa Concurrent error detection in GF(2m) multiplication and its application in elliptic curve cryptography. Search on Bibsonomy IET Circuits, Devices & Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa ASIC Hardware Performance. Search on Bibsonomy The eSTREAM Finalists The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa Price to Provide RFID Security and Privacy?. Search on Bibsonomy SECRYPT The full citation details ... 2008 DBLP  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa Low Area Scalable Montgomery Inversion Over GF(2m). Search on Bibsonomy SECRYPT The full citation details ... 2008 DBLP  BibTeX  RDF
1Mohamed N. Hassan, Mohammed Benaissa An improved Montgomery inversion algorithm over GF(2m) targeted for low area scalable inverter on FPGA. Search on Bibsonomy APCCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Junfeng Chu, Mohammed Benaissa GF(2m) multiplier using Polynomial Residue Number System. Search on Bibsonomy APCCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment). Search on Bibsonomy IET Information Security The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Riyaz A. Patel, Mohammed Benaissa, Said Boussakta Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Modulo 2n-1 adders, One's complement adders, computer arithmetic, VLSI design, parallel-prefix adders
1Riyaz A. Patel, Mohammed Benaissa, Said Boussakta Fast Modulo 2n - (2n-2+1) Addition: A New Class of Adder for RNS. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF modular adder, VLSI, Computer arithmetic, residue number system, parallel-prefix adder
1Riyaz A. Patel, Mohammed Benaissa, Neil Powell, Said Boussakta Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Mohammed Benaissa, Yiqun Zhu Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Mohammed Benaissa, Wei Ming Lim Design of flexible GF(2m) elliptic curve cryptography processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa Very small FPGA application-specific instruction processor for AES. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1William N. Chelton, Mohammed Benaissa High-Speed Pipelined EGG Processor on FPGA. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1William N. Chelton, Mohammed Benaissa Limiting Flexibility in Multiplication over GF(2m): A Design Methodology. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1William N. Chelton, Mohammed Benaissa Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach. Search on Bibsonomy ICECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa AES as stream cipher on a small FPGA. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tim Good, Mohammed Benaissa AES on FPGA from the Fastest to the Smallest. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
1Ashraf Mahran, Mohammed Benaissa Iterative decoding with a hamming threshold for block turbo codes. Search on Bibsonomy IEEE Communications Letters The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Ashraf Mahran, Mohammed Benaissa Adaptive combined Chase-GMD algorithms for block codes. Search on Bibsonomy IEEE Communications Letters The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Mohammed Benaissa, Yiqun Zhu A Novel High-Speed Configurable Viterbi Decoder for Broadband Access. Search on Bibsonomy EURASIP J. Adv. Sig. Proc. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Wei Ming Lim, Mohammed Benaissa Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF GF(2m) arithmetic, forward error control coding, galois field processor, cryptography, advanced encryption standard, elliptic curve cryptography, design space exploration, Reed-Solomon code, hardware-software co-design, BCH code
1Yiqun Zhu, Mohammed Benaissa A novel ACS scheme for area-efficient Viterbi decoders. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Yiqun Zhu, Mohammed Benaissa Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. Search on Bibsonomy ASAP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1A. Mahmudi, Mohammed Benaissa, P. Sweeney, Martin J. N. Sibley On the implementation of soft-decision decoding for RS codes. Search on Bibsonomy PIMRC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1A. Mahmudi, Mohammed Benaissa, P. Sweeney The implementation of generalized minimum distance decoding for Reed Solomon codes. Search on Bibsonomy ISCAS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor On-Line Error Detection for Bit-Serial Multipliers in GF(2m). Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF finite fields, multipliers, parity checking, on-line error detection
1M. G. Parker, Mohammed Benaissa Modular Arithmetic Using Low Order Redundant Bases. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1997 DBLP  DOI  BibTeX  RDF residue and polynomial number systems, Modular arithmetic, redundant number systems, number theoretic transforms
1Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor Finite field inversion over the dual basis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
1Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor GF(2^m) Multiplication and Division Over the Dual Basis. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF finite field division, Reed-Solomon codecs, VLSI, systolic arrays, irreducible polynomials, finite field multiplication, Dual basis
1Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor, J. Luty Programmable bit-serial Reed-Solomon encoders. Search on Bibsonomy EUSIPCO The full citation details ... 1996 DBLP  BibTeX  RDF
1Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa A dual basis bit-serial systolic multiplier for GF(2m). Search on Bibsonomy Integration The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor Bit-Serial Dual Basis Systolic Multipliers for GF 2m. Search on Bibsonomy ISCAS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
1M. G. Parker, Mohammed Benaissa Fault-Tolerant Linear Convolution using Residue Number Systems. Search on Bibsonomy ISCAS The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa A Dual Basis Systolic Divider for GF(2m). Search on Bibsonomy ISCAS The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1M. G. Parker, Mohammed Benaissa Bit-serial, VLSI architecture for the implementation of maximum-length number-theoretic transforms using mixed basis representation. Search on Bibsonomy ICASSP (1) The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #72 of 72 (100 per page; Change: )
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license