| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Lena E. Olson, Mark D. Hill |
Probabilistic Directed Writebacks for Exclusive Caches.  |
SIGARCH Comput. Archit. News  |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao |
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi |
Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryohei Kobayashi, Tomohiro Misono, Kenji Kise |
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Susumu Mashimo, Thiem Van Chu, Kenji Kise |
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shohei Sassa, Kenji Kanazawa, Shaowei Cai 0001, Moritoshi Yasunaga |
An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cuong Pham-Quoc, Biet Nguyen, Tran Ngoc Thinh |
FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Knodel, Paul R. Genssler, Rainer G. Spallek |
Migration of long-running Tasks between Reconfigurable Resources using Virtualization. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Qian Zhao 0001, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chengzhe Li, Lai Yoong Yee, Hiroshi Maruyama, Yoshiki Yamaguchi |
FPGA-based Volleyball Player Tracker. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung |
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Erik H. D'Hollander |
High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars |
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang |
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xusheng Zhan, Yungang Bao, Christian Bienia, Kai Li 0001 |
PARSEC3.0: A Multicore Benchmark Suite with Network Stacks and SPLASH-2X. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiayi Sheng, Qingqing Xiong, Chen Yang 0010, Martin C. Herbordt |
Collective Communication on FPGA Clusters with Static Scheduling. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinod Pangracious, Mulhim Al-Doori |
Novel Three-Dimensional Embedded FPGA Technology and Achitecture. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hadi Asgharimoghaddam, Nam Sung Kim |
SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Fatemeh Eslami, Steven J. E. Wilton |
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. |
SIGARCH Comput. Archit. News |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav Sedukhin |
Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Mefenza, Nicolas Edwards, Christophe Bobda |
Interface Based Memory Synthesis of Image Processing Applications in FPGA. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk |
Parallel Genetic Algorithms on Multiple FPGAs. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Al-Wattar, Shawki Areibi, Gary William Grewal |
Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | David de la Chevallerie, Jens Korinth, Andreas Koch 0001 |
ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Soukaina N. Hmid, José Gabriel F. Coutinho, Wayne Luk |
A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Momeni, Hamed Tabkhi, Yash Ukidave, Gunar Schirner, David R. Kaeli |
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Koji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri |
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani |
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura |
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Da Tong, Viktor K. Prasanna |
High Throughput Sketch Based Online Heavy Hitter Detection on FPGA. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati |
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Lashgar, Ebad Salehi, Amirali Baniasadi |
A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling Resources. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano |
Breadth First Search on Cost-efficient Multi-GPU Systems. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinying Wang 0004, Phillip H. Jones, Joseph Zambreno |
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell |
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. |
SIGARCH Comput. Archit. News |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Diana Göhringer |
Reconfigurable Multiprocessor Systems: Handling Hydras Heads - A Survey. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda |
A Case Study of FPGA Blokus Duo Solver by System-Level Design. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mioara Joldes, Valentina Popescu, Warwick Tucker |
Searching for Sinks for the Hénon Map using a Multipleprecision GPU Arithmetic Library. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Núñez-Yáñez |
Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri |
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift |
BadgerTrap: a tool to instrument x86-64 TLB misses. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Wang 0004, Guangyu Sun 0003, Jiahua Chen, Jian Gong, Haoyang Wu, Xiaoguang Li, Songwu Lu, Jason Cong |
GRT: A Reconfigurable SDR Platform with High Performance and Usability. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet Nuggets. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato |
PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Atin Mukherjee 0002, Amitabha Sinha, Debesh Choudhury |
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Haruhisa Tsuyama, Tsutomu Maruyama |
GPU and FPGA Acceleration of Level Set Method. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shin Morishima, Hiroki Matsutani |
Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano |
Accelerating Breadth First Search on GPU-BOX. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Subijit Mondal, Subhashis Maitra |
Data security-modified AES algorithm and its applications. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumik Sen, Subhashis Maitra |
Three levels three dimensional compact coding. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | César Torres-Huitzil, Marco Aurelio Nuño-Maganda |
Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shimpei Nomura, Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano |
Performance Analysis of the Multi-GPU System with ExpEther. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian, Bingxing Liu, Yuhui Deng |
Balancing disk access times in RAID5 disk arrays in degraded mode by conditionally prioritizing fork/join requests. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Tanabe, Tsutomu Maruyama |
Fast and Accurate Optical Flow Estimation using FPGA. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Louis Lafitte |
Entangled-Coupling. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsuyoshi Watanabe, Naohito Nakasato |
GPU Accelerated Hybrid Tree Algorithm for Collision Less N-body Simulations. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Ryotaro Chiba, Tomoya Ueno, Hayato Suzuki, Ryo Ito, Satoru Yamamoto |
FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation with Building Cube Method. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Florent de Dinechin, Matei Istoan, Guillaume Sergent |
Fixed-point trigonometric functions on FPGAs. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Jubee Tada |
Performance evaluation of 3-D stacked 32-bit parallel multipliers. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Maitra, Amitabha Sinha |
High performance MAC unit for DSP and cryptographic applications. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha |
Performance analysis of a FPGA based novel binary and DBNS multiplier. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Amrita Saha, Pijush Biswas, Amitabha Sinha |
An integrated development platform of a reconfigurable radio processor for software defined radio. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont |
Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Gary Plumbridge, Jack Whitham, Neil C. Audsley |
Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Wim Vanderbauwhede, Anton Frolov 0002, Sai Rahul Chalamalasetti, Martin Margala |
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Maitra, Amitabha Sinha |
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuichiro Tanaka, Shimpei Sato, Kenji Kise |
The Ultrasmall soft processor. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Heiner Giefers, Christian Plessl, Jens Förstner |
Accelerating finite difference time domain simulations with reconfigurable dataflow computers. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Atabak Mahram, Martin C. Herbordt |
NCBI BLASTP on the convey HC1-EX. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty |
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Sartin-Tarm, Tony Nowatzki, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan |
Constraint centric scheduling guide. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Godard |
The Mill: split-stream encoding. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno, Kyo Koizumi, Satoru Yamamoto |
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba |
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Liucheng Guo, David B. Thomas, Wayne Luk |
Customisable architectures for the set covering problem. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Kun Tseng, FuFu Zeng, Huang-Nan Huang, Yiming Liu, Jeng-Shyang Pan 0001, W. H. Ip, Chun-Hua Wu |
A new non-exact Aho-Corasick framework for ECG classification. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Santanu Pal, Amitabha Sinha, Pijush Biswas |
FPGA implementation of a novel DCT architecture reducing constant cosine terms. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomislav Janjusic, Krishna M. Kavi |
Gleipnir: a memory profiling and tracing tool. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Apala Guha, Yao Zhang, Raihan Ur Rasool, Andrew A. Chien |
Systematic evaluation of workload clustering for extremely energy-efficient architectures. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Maitra, Amitabha Sinha |
Design and simulation of MAC unit using combinational circuit and adder. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Hong, Khaled Benkrid, Mohd Nazrin Md. Isa, Xabier Iturbe |
A run-time reconfigurable system for adaptive high performance efficient computing. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi |
A reconfigurable Java accelerator with software compatibility for embedded systems. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Thomasian |
Disk arrays with multiple RAID levels. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski |
Accelerating sequential Monte Carlo method for real-time air traffic management. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Thorson |
Internet nuggets. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha |
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Maitra, Amitabha Sinha |
A new algorithm for computing triple-base number system. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung |
Roberts: reconfigurable platform for benchmarking real-time systems. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Sano, Yoshiaki Kono |
FPGA-based Connect6 solver with hardware-accelerated move refinement. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeshi Kakimoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri |
Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheng Zhi Shun, Tsutomu Maruyama |
FPGA acceleration of CDO pricing based on correlation expansions. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcos K. Aguilera, Dahlia Malkhi, Keith Marzullo, Alessandro Panconesi, Andrzej Pelc, Roger Wattenhofer |
Announcing the 2012 Edsger W. Dijkstra prize in distributed computing. |
SIGARCH Comput. Archit. News |
2012 |
DBLP DOI BibTeX RDF |
|
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