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Publications at "SIGARCH Computer Architecture News"( http://dblp.L3S.de/Venues/SIGARCH_Computer_Architecture_News )

URL (DBLP): http://dblp.uni-trier.de/db/journals/sigarch

Publication years (Num. hits)
1991 (52) 1992 (22) 1993 (31) 1994 (35) 1995 (21) 1996 (22) 1997 (20) 1998-1999 (40) 2000-2001 (44) 2002 (16) 2003 (25) 2004 (16) 2005 (63) 2006 (20) 2007 (51) 2008 (25) 2009 (17) 2010 (23) 2011 (35) 2012 (29) 2013 (30) 2014 (24) 2015 (19) 2016 (20)
Publication types (Num. hits)
article(700)
Venues (Conferences, Journals, ...)
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Found 700 publication records. Showing 700 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Xusheng Zhan, Yungang Bao, Christian Bienia, Kai Li 0001 PARSEC3.0: A Multicore Benchmark Suite with Network Stacks and SPLASH-2X. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hadi Asgharimoghaddam, Nam Sung Kim SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Cuong Pham-Quoc, Biet Nguyen, Tran Ngoc Thinh FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Oliver Knodel, Paul R. Genssler, Rainer G. Spallek Migration of long-running Tasks between Reconfigurable Resources using Virtualization. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vinod Pangracious, Mulhim Al-Doori Novel Three-Dimensional Embedded FPGA Technology and Achitecture. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Erik H. D'Hollander High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Fatemeh Eslami, Steven J. E. Wilton An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Susumu Mashimo, Thiem Van Chu, Kenji Kise Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shohei Sassa, Kenji Kanazawa, Shaowei Cai, Moritoshi Yasunaga An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Chengzhe Li, Lai Yoong Yee, Hiroshi Maruyama, Yoshiki Yamaguchi FPGA-based Volleyball Player Tracker. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Qian Zhao 0001, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi A Study of Heterogeneous Computing Design Method based on Virtualization Technology. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jiayi Sheng, Qingqing Xiong, Chen Yang, Martin C. Herbordt Collective Communication on FPGA Clusters with Static Scheduling. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Lena E. Olson, Mark D. Hill Probabilistic Directed Writebacks for Exclusive Caches. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ryohei Kobayashi, Tomohiro Misono, Kenji Kise A High-speed Verilog HDL Simulation Method using a Lightweight Translator. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav Sedukhin Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Xinying Wang, Phillip H. Jones, Joseph Zambreno A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1David de la Chevallerie, Jens Korinth, Andreas Koch 0001 ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Koji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Amir Momeni, Hamed Tabkhi, Yash Ukidave, Gunar Schirner, David R. Kaeli Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ahmed Al-Wattar, Shawki Areibi, Gary William Grewal Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Ahmad Lashgar, Ebad Salehi, Amirali Baniasadi A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling Resources. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Da Tong, Viktor K. Prasanna High Throughput Sketch Based Online Heavy Hitter Detection on FPGA. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati 10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano Breadth First Search on Cost-efficient Multi-GPU Systems. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk Parallel Genetic Algorithms on Multiple FPGAs. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Soukaina N. Hmid, José Gabriel F. Coutinho, Wayne Luk A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Michael Mefenza, Nicolas Edwards, Christophe Bobda Interface Based Memory Synthesis of Image Processing Applications in FPGA. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jean-Louis Lafitte Entangled-Coupling. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Diana Göhringer Reconfigurable Multiprocessor Systems: Handling Hydras Heads - A Survey. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1César Torres-Huitzil, Marco Aurelio Nuño-Maganda Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Soumik Sen, Subhashis Maitra Three levels three dimensional compact coding. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Shimpei Nomura, Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano Performance Analysis of the Multi-GPU System with ExpEther. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yu Tanabe, Tsutomu Maruyama Fast and Accurate Optical Flow Estimation using FPGA. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda A Case Study of FPGA Blokus Duo Solver by System-Level Design. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Rie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Subijit Mondal, Subhashis Maitra Data security-modified AES algorithm and its applications. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Tao Wang 0004, Guangyu Sun, Jiahua Chen, Jian Gong, Haoyang Wu, Xiaoguang Li, Songwu Lu, Jason Cong GRT: A Reconfigurable SDR Platform with High Performance and Usability. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Shin Morishima, Hiroki Matsutani Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano Accelerating Breadth First Search on GPU-BOX. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1José L. Núñez-Yáñez Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Atin Mukherjee 0002, Amitabha Sinha, Debesh Choudhury A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Kentaro Sano, Ryotaro Chiba, Tomoya Ueno, Hayato Suzuki, Ryo Ito, Satoru Yamamoto FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation with Building Cube Method. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Haruhisa Tsuyama, Tsutomu Maruyama GPU and FPGA Acceleration of Level Set Method. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Alexander Thomasian, Bingxing Liu, Yuhui Deng Balancing disk access times in RAID5 disk arrays in degraded mode by conditionally prioritizing fork/join requests. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mioara Joldes, Valentina Popescu, Warwick Tucker Searching for Sinks for the Hénon Map using a Multipleprecision GPU Arithmetic Library. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Tsuyoshi Watanabe, Naohito Nakasato GPU Accelerated Hybrid Tree Algorithm for Collision Less N-body Simulations. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet Nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift BadgerTrap: a tool to instrument x86-64 TLB misses. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno, Kyo Koizumi, Satoru Yamamoto Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Michael Sartin-Tarm, Tony Nowatzki, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan Constraint centric scheduling guide. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Liucheng Guo, David B. Thomas, Wayne Luk Customisable architectures for the set covering problem. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi A reconfigurable Java accelerator with software compatibility for embedded systems. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Chuan Hong, Khaled Benkrid, Mohd Nazrin Md. Isa, Xabier Iturbe A run-time reconfigurable system for adaptive high performance efficient computing. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Santanu Pal, Amitabha Sinha, Pijush Biswas FPGA implementation of a novel DCT architecture reducing constant cosine terms. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Heiner Giefers, Christian Plessl, Jens Förstner Accelerating finite difference time domain simulations with reconfigurable dataflow computers. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Florent de Dinechin, Matei Istoan, Guillaume Sergent Fixed-point trigonometric functions on FPGAs. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Subhashis Maitra, Amitabha Sinha Design and simulation of MAC unit using combinational circuit and adder. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Subhashis Maitra, Amitabha Sinha High performance MAC unit for DSP and cryptographic applications. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski Accelerating sequential Monte Carlo method for real-time air traffic management. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Alexander Thomasian Disk arrays with multiple RAID levels. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Amrita Saha, Pijush Biswas, Amitabha Sinha An integrated development platform of a reconfigurable radio processor for software defined radio. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yuichiro Tanaka, Shimpei Sato, Kenji Kise The Ultrasmall soft processor. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kuo-Kun Tseng, FuFu Zeng, Huang-Nan Huang, Yiming Liu, Jeng-Shyang Pan, W. H. Ip, Chun-Hua Wu A new non-exact Aho-Corasick framework for ECG classification. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha Performance analysis of a FPGA based novel binary and DBNS multiplier. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Atabak Mahram, Martin C. Herbordt NCBI BLASTP on the convey HC1-EX. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Apala Guha, Yao Zhang, Raihan Ur Rasool, Andrew A. Chien Systematic evaluation of workload clustering for extremely energy-efficient architectures. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ivan Godard The Mill: split-stream encoding. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Gary Plumbridge, Jack Whitham, Neil C. Audsley Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Jubee Tada Performance evaluation of 3-D stacked 32-bit parallel multipliers. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Subhashis Maitra, Amitabha Sinha High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Tomislav Janjusic, Krishna M. Kavi Gleipnir: a memory profiling and tracing tool. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Mark Thorson Internet nuggets. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton Efficient architecture and scheduling technique for pairwise sequence alignment. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Nishant Kumar Giri, Amitabha Sinha FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada High performance phylogenetic analysis on CUDA-compatible GPUs. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jamshaid Sarwar Malik, Paolo Palazzari, Ahmed Hemani Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao On a wideband fast fourier transform for a radio telescope. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Conrad Mueller Axiom based architecture. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
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