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Publications of "Shunji Kimura" ( )

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Publication years (Num. hits)
1999-2018 (9)
Publication types (Num. hits)
article(2) inproceedings(7)
Venues (Conferences, Journals, ...)
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Found 10 publication records. Showing 9 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu Throughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems. Search on Bibsonomy PIMRC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura Hardware accelerator for coordinated radioresource scheduling in 5G ultra-high-density distributed antenna systems. Search on Bibsonomy ITNAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. Search on Bibsonomy A-SSCC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Yumiko Senoo, Shin Kaneko, Shunji Kimura, Naoto Yoshimoto Wavelength router for energy efficient photonic aggregation with large-scale λ-tunable WDM/TDM-PON. Search on Bibsonomy APCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Kazutaka Hara, Shunji Kimura, Hirotaka Nakamura, Naoto Yoshimoto, Hisaya Hadama Ultra Fast Response AC-Coupled Burst-Mode Receiver with High Sensitivity and Wide Dynamic Range for 10G-EPON System. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs. Search on Bibsonomy IEICE Transactions The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Shunji Kimura, T. Otsuji, H. Kikuchi, K. Murata, E. Sano Circuit design technologies for high-speed lightwave communications beyond 40 Gbit/s. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
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