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Publications of "Tanay Karnik" ( http://dblp.L3S.de/Authors/Tanay_Karnik )

  Author page on DBLP  Author page in RDF  Community of Tanay Karnik in ASPL-2

Publication years (Num. hits)
1994-2006 (16) 2007-2009 (17) 2010-2012 (19) 2013-2018 (16) 2019 (1)
Publication types (Num. hits)
article(25) incollection(1) inproceedings(41) proceedings(2)
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Found 70 publication records. Showing 69 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Helen Li, Jae-sun Seo, Chang Song Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. Search on Bibsonomy IEEE J. Emerg. Sel. Topics Circuits Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Arindam Basu, Meng-Fan Chang, Elisabetta Chicca, Tanay Karnik, Hai Helen Li, Jae-sun Seo Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. Search on Bibsonomy IEEE J. Emerg. Sel. Topics Circuits Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Suhwan Kim, Vaibhav Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James Tschanz, Vivek De A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. Search on Bibsonomy VLSI Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao 0002, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. Search on Bibsonomy ISSCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. Search on Bibsonomy ISCA The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tanay Karnik Technology trends, requirements and challenges for ubiquitous self-powered IOT systems deployment. Search on Bibsonomy IGSC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Stacey Weber Jackson Editorial. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. Search on Bibsonomy JETC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, James Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar Resiliency for many-core system on a chip. Search on Bibsonomy ASP-DAC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yuan Xie 0001, Tanay Karnik, Muhammad M. Khellah, Renu Mehra (eds.) International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 Search on Bibsonomy ISLPED The full citation details ... 2014 DBLP  BibTeX  RDF
1Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De Adaptive and Resilient Circuits for Dynamic Variation Tolerance. Search on Bibsonomy IEEE Design & Test The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner F5: Frequency generation and clock distribution. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Mondira (Mandy) Pant, Shekhar Borkar Power management and delivery for high-performance microprocessors. Search on Bibsonomy DAC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Pai H. Chou, Ru Huang, Yuan Xie 0001, Tanay Karnik (eds.) International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 Search on Bibsonomy ISLPED The full citation details ... 2013 DBLP  BibTeX  RDF
1Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz A 22nm dynamically adaptive clock distribution for voltage droop tolerance. Search on Bibsonomy VLSIC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky Design for test and reliability in ultimate CMOS. Search on Bibsonomy DATE The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held Scaling the "Memory Wall": Designer track. Search on Bibsonomy ICCAD The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. Search on Bibsonomy IEEE J. Emerg. Sel. Topics Circuits Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Paul D. Franzon, W. Rhett Davis, Zheng Zhou 0004, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas Coordinating 3D designs: Interface IP, standards or free form? Search on Bibsonomy 3DIC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar 3DICs for tera-scale computing: a case study. Search on Bibsonomy ISPD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. Search on Bibsonomy ISSCC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. Search on Bibsonomy ISSCC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. Search on Bibsonomy CICC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. Search on Bibsonomy CICC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De Resilient design in scaled CMOS for energy efficiency. Search on Bibsonomy ASP-DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De Resilient microprocessor design for high performance & energy efficiency. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF resilient design
1DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De SRAM dynamic stability estimation using MPFP and its applications. Search on Bibsonomy Microelectronics Journal The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi 2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Pengfei Li 0001, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar Circuit techniques for dynamic variation tolerance. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
1James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik Resilient circuits - Enabling energy-efficient performance and reliability. Search on Bibsonomy ICCAD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De Accurate Estimation of SRAM Dynamic Stability. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Hao Yu 0001, Yiyu Shi, Lei He 0001, Tanay Karnik Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James Tschanz, Vivek De, Tanay Karnik, Greg Taylor A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi 2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De Analytical Model for the Propagation Delay of Through Silicon Vias. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 3D integrated circuits, propagation delay model, dimensional analysis, TSV
1Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1James Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik Low Voltage Buffered Bandgap Reference. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Ruchir Puri, Tanay Karnik, Rajiv V. Joshi Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner High-frequency DC-DC conversion : fact or fiction. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He 0001, Tanay Karnik Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF DC/DC conversion, zero voltage switching
1Hao Yu 0001, Yiyu Shi, Lei He 0001, Tanay Karnik Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SQP optimization, structured and parameterized macromodel, thermal management and simulation
1Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang Logic soft errors in sub-65nm technologies design and CAD challenges. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF architectural vulnerability factor, built-in soft error resilience, derating, error blocking, error detection, recovery, soft error
1Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi Design of sub-90nm Circuits and Design Methodologies. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Peter Hazucha, Jagdish Patel Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. Search on Bibsonomy IEEE Trans. Dependable Sec. Comput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF reliability, High performance, soft error, error tolerance, single event upset
1Shekhar Borkar, Tanay Karnik, Vivek De Design and reliability challenges in nanometer technologies. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF leakage tolerance, reliability, low-power, variability, soft errors, circuits, SEU, SER, variation tolerance
1Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik HiSIM: hierarchical interconnect-centric circuit simulator. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration
1Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De Parameter variations and impact on circuits and microarchitecture. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF high performance deisgn, parameter variation, body bias
1Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Dual-Vt design, multiple threshold, optimization, sizing
1Tanay Karnik, Shekhar Borkar, Vivek De Sub-90nm technologies: challenges and opportunities for CAD. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Tanay Karnik Microprocessor Layout Method. Search on Bibsonomy The VLSI Handbook The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Tanay Karnik, Sung-Mo Kang An empirical model for accurate estimation of routing delay in FPGAs. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Routing Delay, Modeling, FPGA, Estimation, Statistics
1Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab Structural and behavioral synthesis for testability techniques. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
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