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Publications of Víctor H. Champac Víctor H. Champac Vilela ( http://dblp.L3S.de/Authors/Víctor_H._Champac )

URL (Homepage):  http://www-elec.inaoep.mx/espanol/personal/investigadores/champac.html  Author page on DBLP  Author page in RDF  Community of Víctor H. Champac in ASPL-2

Publication years (Num. hits)
1991-2004 (19) 2005-2011 (18) 2012-2015 (19) 2016-2018 (15) 2019 (5)
Publication types (Num. hits)
article(30) inproceedings(46)
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The graphs summarize 20 occurrences of 17 keywords

Results
Found 77 publication records. Showing 76 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac Modeling and Detectability of Full Open Gate Defects in FinFET Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. Search on Bibsonomy J. Electronic Testing The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Michel Renovell, Víctor H. Champac B-open: A New Defect in Nanometer Technologies due to SADP Process. Search on Bibsonomy ETS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1I. D. Meza-Ibarra, Víctor H. Champac, R. Gómez-Fuentes, J. R. Noriega, A. Vera-Marquina Identification of Logic Paths Influenced by Severe Coupling Capacitances. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. Search on Bibsonomy LATS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. Search on Bibsonomy J. Electronic Testing The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Zahira Perez, Hector Villacorta, Víctor H. Champac An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. Search on Bibsonomy VLSI-SoC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. Search on Bibsonomy VLSI-SoC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Roberto Gómez, Víctor H. Champac A metric-guided gate-sizing methodology for aging guardband reduction. Search on Bibsonomy LATS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Jean Marc Gallière, Michel Renovell, Víctor H. Champac Analysis of short defects in FinFET based logic cells. Search on Bibsonomy LATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Michel Renovell, Víctor H. Champac Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Jaume Segura 0001, Víctor H. Champac Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. Search on Bibsonomy J. Electronic Testing The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Andres F. Gomez, Víctor H. Champac Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. Search on Bibsonomy J. Low Power Electronics The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Felipe Lavratti, Guilherme Medeiros Machado, M. Sartori, Letícia Maria Veiras Bolzani, Víctor H. Champac, Fabian Vargas Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Search on Bibsonomy Microelectronics Reliability The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. Search on Bibsonomy EWDTS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac Behavior and test of open-gate defects in FinFET based cells. Search on Bibsonomy ETS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Freddy Forero, Andres F. Gomez, Víctor H. Champac A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. Search on Bibsonomy LATS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura 0001, Víctor H. Champac Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Search on Bibsonomy Microelectronics Journal The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac Screening small-delay defects using inter-path correlation to reduce reliability risk. Search on Bibsonomy Microelectronics Reliability The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. Search on Bibsonomy VLSI-SoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez Circuit performance optimization for local intra-die process variations using a gate selection metric. Search on Bibsonomy VLSI-SoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Víctor H. Champac Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. Search on Bibsonomy LATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal Message from the LATS2015 Chairs. Search on Bibsonomy LATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura 0001, Víctor H. Champac Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. Search on Bibsonomy LATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. Search on Bibsonomy VTS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras Skew violation verification in digital interconnect signals based on signal addition. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. Search on Bibsonomy LATW The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1C. J. Clark, Víctor H. Champac Hot topic session 12B: Stay relevant with standards-based DFT. Search on Bibsonomy VTS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. Search on Bibsonomy J. Electronic Testing The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura 0001, Roberto Gómez Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. Search on Bibsonomy IEEE Design & Test The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura 0001 Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. Search on Bibsonomy LATW The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura 0001 Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test. Search on Bibsonomy Microelectronics Reliability The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez, Chuck Hawkins, Jaume Segura 0001 Testing of Stuck-Open Faults in Nanometer Technologies. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jackson Pachito, Celestino V. Martins, B. Jacinto, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Víctor H. Champac, Michel Renovell Low voltage testing for interconnect opens under process variations. Search on Bibsonomy LATW The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu Small-delay defects detection under process variation using Inter-Path Correlation. Search on Bibsonomy VTS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jose Luis Garcia-Gervacio, Víctor H. Champac Computing the Detection Probability for Small Delay Defects of Nanometer ICs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. Search on Bibsonomy J. Low Power Electronics The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesus Moreno, Víctor H. Champac, Michel Renovell A new methodology for realistic open defect detection probability evaluation under process variations. Search on Bibsonomy VTS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. Search on Bibsonomy VTS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Victor Avendaño, Joan Figueras Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira Programmable aging sensor for automotive safety-critical applications. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Jose Luis Garcia-Gervacio, Víctor H. Champac Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. Search on Bibsonomy European Test Symposium The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis 0001, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira Predictive error detection by on-line aging monitoring. Search on Bibsonomy IOLTS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis 0001, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira Low-sensitivity to process variations aging sensor for automotive safety-critical applications. Search on Bibsonomy VTS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Jose Luis Garcia-Gervacio, Víctor H. Champac Detectability analysis of small delays due to resistive opens considering process variations. Search on Bibsonomy IOLTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis 0001, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira Built-in aging monitoring for safety-critical applications. Search on Bibsonomy IOLTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura 0001 Stuck-Open Fault Leakage and Testing in Nanometer Technologies. Search on Bibsonomy VTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Roberto Gómez, Alejandro Girón, Víctor H. Champac A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. Search on Bibsonomy J. Electronic Testing The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
1Nestor Hernandez, Víctor H. Champac Testing Skew and Logic Faults in SoC Interconnects. Search on Bibsonomy ISVLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac A design methodology for logic paths tolerant to local intra-die variations. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Antonio Zenteno, José L. Garcia Testing of resistive opens in CMOS latches and flip-flops. Search on Bibsonomy European Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Roberto Gómez, Alejandro Girón, Víctor H. Champac Test of Interconnection Opens Considering Coupling Signals. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Fabian Vargas, Víctor H. Champac Guest Editorial. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Victor Avendaño, Víctor H. Champac, Joan Figueras Signal integrity verification using high speed monitors. Search on Bibsonomy European Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs Analysis and Attenuation Proposal in Ground Bounce. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela The noise immunity of dynamic digital circuits with technology scaling. Search on Bibsonomy ISCAS (2) The full citation details ... 2004 DBLP  BibTeX  RDF
1Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela An improved technique to increase noise-tolerance in dynamic digital circuits. Search on Bibsonomy ISCAS (2) The full citation details ... 2004 DBLP  BibTeX  RDF
1Víctor H. Champac, Ingrid Jansch-Pôrto Guest Editorial. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac, Alejandro Díaz-Sánchez A new technique for noise-tolerant pipelined dynamic digital circuits. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Marcelo Lubaszewski, Víctor H. Champac Guest Editorial. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Antonio Zenteno, Víctor H. Champac, Joan Figueras Detectability Conditions of Full Opens in the Interconnections. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF logic testing, IDDQ testing, opens, defect modeling
1Antonio Zenteno, Víctor H. Champac Resistive Opens in a Class of CMOS Latches: Analysis and DFT. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Gordana Jovanovic-Dolecek, Víctor H. Champac CGTDEMO - educational software for the central limit theorem. Search on Bibsonomy SIGCSE Bulletin The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Antonio Zenteno Detectability Conditions for Interconnection Open Defect. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, José Castillejos, Joan Figueras IDDQ Testing of Opens in CMOS SRAMs. Search on Bibsonomy J. Electronic Testing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF data retention faults, memory testing, opens, IDDQ
1Víctor H. Champac, José Castillejos, Joan Figueras IDDQ Testing of Opens in CMOS SRAMs. Search on Bibsonomy VTS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Joan Figueras Testability of floating gate defects in sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
1Víctor H. Champac, Antonio Rubio, Joan Figueras Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
1Víctor H. Champac, Antonio Rubio, Joan Figueras Analysis of the Floating Gate Defect in CMOS. Search on Bibsonomy DFT The full citation details ... 1993 DBLP  BibTeX  RDF
1Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio Quiescent current analysis and experimentation of defective CMOS circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1992 DBLP  DOI  BibTeX  RDF Bridging failures, floating gate opens, intentionally designed defective circuits defects, current testing, defect modeling, gate oxide shorts
1Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. Search on Bibsonomy ITC The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
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