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Publication years (Num. hits)
1983-1988 (21) 1989-1990 (36) 1991 (18) 1992 (53) 1993 (131) 1994 (63) 1995 (156) 1996 (149) 1997 (73) 1998 (79) 1999 (103) 2000 (83) 2001 (68) 2002 (98) 2003 (125) 2004 (120) 2005 (107) 2006 (133) 2007 (103) 2008 (107) 2009 (67) 2010 (36) 2011 (25) 2012-2013 (36) 2014 (23) 2015-2016 (15) 2017-2019 (12)
Publication types (Num. hits)
article(291) book(8) incollection(11) inproceedings(1699) phdthesis(28) proceedings(3)
Venues (Conferences, Journals, ...)
EURO-DAC(337) DATE(84) DAC(69) FPL(58) FDL(46) IEEE Design & Test of Computer...(34) VLSI Design(33) FCCM(28) FPGA(27) ISCAS(24) VLSI Signal Processing(24) DFT(23) EUROMICRO(23) ICCAD(20) MSE(20) DSD(19) More (+10 of total 453)
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Found 2040 publication records. Showing 2040 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
141Sumit Ghosh In Search of the Origin of VHDL's Delta Delays. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs
103Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden Improving Design and Verification Productivity with VHDL-200x. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
95Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey VHDL semantics and validating transformations. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
87Ranga Vemuri, R. Kalyanaraman Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
84Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum Program slicing for VHDL. Search on Bibsonomy STTT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
75Sumit Ghosh P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
75Sheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey A Semantic Model of VHDL for Validating Rewriting Algebras. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF rewriting algebras validation, declarative style, process-folding, CAD tool optimization, VHDL, formal model, semantic model, hardware description languages, interval temporal logic, dynamic semantics
75Nelson L. Passos, Edwin Hsing-Mean Sha Synthesis of Multi-Dimensional Applications in VHDL. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Multidimensional Loops, Scheduling, VHDL, Circuit Optimization, Address generation
72Wilco Van Hoogstraeten, Henk Corporaal ADVISE: Performance Evaluation of Parallel VHDL Simulation. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF VHDL compilation, VHDL simulation, partitioning, distributed simulation, Optimistic simulation, multiprocessor simulation
70Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu Verification of VHDL Designs Using VAL. Search on Bibsonomy DAC The full citation details ... 1988 DBLP  BibTeX  RDF
67Abdulhadi Shoufan, Zheng Lu, Guido Rößling A platform for visualizing digital circuit synthesis with VHDL. Search on Bibsonomy ITiCSE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF digital circuit synthesis, visualization, animation, VHDL
62Alex Doboli, Ranga Vemuri Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
62Basant Rajan, R. K. Shyamasundar Modeling VHDL in Multiclock ESTEREL. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
62Shenggao Li, Brian Okoon, Mona Mostafa Hella, Mohammed Ismail, Maya Rubeiz The Implementation of a VHDL-AMS to SPICE Converter. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
62Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
54Daniel Köb, Bernhard Peischl, Franz Wotawa Debugging VHDL Designs Using Temporal Process Instances. Search on Bibsonomy IEA/AIE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF debugging of hardware designs, model-based diagnosis, software debugging
54Dragos Lungeanu, C.-J. Richard Shi Parallel and Distributed VHDL Simulation. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
54Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
54Gábor Hosszú, Ferenc Kovács, László Varga Design procedure based on VHDL language transformations. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
54Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. Search on Bibsonomy EUROMICRO The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
54Petru Eles, Zebo Peng, Alexa Doboli VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. Search on Bibsonomy CODES The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
54David R. Coelho VHDL: A Call for Standards. Search on Bibsonomy DAC The full citation details ... 1988 DBLP  BibTeX  RDF
54Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read The Role of VHDL in the MCC CAD System. Search on Bibsonomy DAC The full citation details ... 1988 DBLP  BibTeX  RDF
54Perry Alexander, Murali Rangarajan, Phillip Baraona A Brief Summary of VSPEC. Search on Bibsonomy World Congress on Formal Methods The full citation details ... 1999 DBLP  DOI  BibTeX  RDF VHDL, languages, systems level design, notations, Larch
51Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF C-to-VHDL compiling, Impulse-C, Smart buffer, FPGA, High-performance computing
51Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee Automatic Parallelization of Compiled Event Driven VHDL Simulation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF scheduling, partitioning, VHDL, multithreading, automatic parallelization, event driven simulation, compiled simulation
51Haifeng Zhou, Zhenghui Lin, Wei Cao Research on VHDL RTL Synthesis System. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
51B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante New Techniques for Accelerating Fault Injection in VHDL Descriptions. Search on Bibsonomy IOLTW The full citation details ... 2000 DBLP  DOI  BibTeX  RDF VHDL, Fault Injection
51Stanislaw Deniziak, Krzysztof Sapiecha High Level Testbench Generation for VHDL Models. Search on Bibsonomy ECBS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF simulation, VHDL, testbench
51Eduard Moser, Norbert Mittwollen VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Mixed-Domain Modelling, Mixed-Domain Simulation, Automotive Engineering, VHDL-AMS
51Michael Mrva Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF object-oriented, VHDL, hardware description language
51Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF timed logic, formal verification, refinement, VHDL, denotational semantics, digital circuits, program logic
51Come Rozon On the Use of VHDL as a Multi-Valued Logic Simulator. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
49A. Sriram, Fadi J. Kurdahi Behavioral Modeling of an ATM Switch using SpecCharts. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
48Peter F. A. Middelhoek, Sreeranga P. Rajan From VHDL to efficient and first-time-right designs: a formal approach. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
48Mark Genoe, Paul Vanoostende, Geert van Wauwe On the use of VHDL-based behavioral synthesis for telecom ASIC design. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
46François Pêcheux, Christophe Lallement, Alain Vachoux VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Medard Rieder, Rico Steiner, Cathy Berthouzoz, Francois Corthay, Thomas Sterren Synthesized UML, a Practical Approach to Map UML to VHDL. Search on Bibsonomy RISE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Franz Wotawa Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results. Search on Bibsonomy Appl. Intell. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF debugging hardware designs, modeling for diagnosis, model-based diagnosis
46J. A. Lopez, Ginés Doménech, R. Ruiz, Tom J. Kazmierski Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang A mixed-signal simulator for VHDL-AMS. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Alessandro Fin, Franco Fummi A VHDL Error Simulator for Functional Test Generation. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
46Peter A. Walker, Sumit Ghosh On the nature and inadequacies of transport timing delay constructs in VHDL descriptions. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
46Frank Vahid, Sanjiv Narayan, Daniel D. Gajski SpecCharts: a VHDL front-end for embedded systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Allen Dewey, Aart J. de Geus VHDL: Toward a Unified View of Design. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
46David R. Coelho A VHDL Standard Package for Logic Modeling. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
46Moon-Jung Chung, Sangchul Kim An Object-Oriented VHDL Design Environment. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
46P. C. Ward, James R. Armstrong Behavioral Fault Simulation in VHDL. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
46Moe Shahdad An Interface between VHDL and EDIF. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
46Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level
43Paul Salama, Maher E. Rizkalla, Michael Eckbauer VHDL Implementation of the Fast Wavelet Transform. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Mallat's fast Wavelet Transform, VHDL implementation, VLSI, finite state machine, discrete wavelet transform
43Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis
43C. T. Carr, T. Martin McGinnity, L. J. McDaid Integration of UML and VHDL-AMS for analogue system modelling. Search on Bibsonomy Formal Asp. Comput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Analogue, Automated mapping, UML, Circuits, VHDL-AMS
43Régis Leveugle, K. Hadjiat Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF VHDL, fault injection, VLSI design, dependability analysis, digital circuits
43William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza Early estimation of the size of VHDL projects. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF VHDL analysis, embedded systems, cost estimation, system-level design, design metrics
43Frédéric Mallet, Daniel Gaffé, Fernand Boéri Concurrent Control Systems: From Grafcet to VHDL. Search on Bibsonomy EUROMICRO The full citation details ... 2000 DBLP  DOI  BibTeX  RDF GRAFCET, programmable components, Modelling, FPGA, Specification, VHDL
43Nouma Izeboudjen, Ahcene Farah, S. Titri, H. Boumeridja Digital Implementation of Artificial Neural Networks: From VHDL Description to EPGA Implementation. Search on Bibsonomy IWANN (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF parametric description, ANN, VHDL, FPGA implementation, top down design
43William E. McUmber, Betty H. C. Cheng UML-Based Analysis of Embedded Systems Using a Mapping to VHDL. Search on Bibsonomy HASE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF formal specifications, mappings, VHDL, Object-oriented modeling
43Jason Coppens, Dhamin Al-Khalili, Come Rozon VHDL Modelling and Analysis of Fault Secure Systems. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Verification, VHDL, Defect Modelling, Fault Security
43Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba VHDL Teamwork, Organization Units and Workspace Management. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF VHDL analysis, simulation, management, Teamwork, cooperative work, workspace, elaboration
43Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen The Design of an Asynchronous VHDL Synthesizer. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Synthesis, VHDL, Asynchronous
43Edwin Naroska Parallel VHDL Simulation. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Conservative Parallel VHDL simulation, parallel discrete event simulation, PDES
43Matthias Mutz Register Transfer Level VHDL Models without Clocks. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF VHDL RT subset, register transfer level models
43Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. Search on Bibsonomy ACSD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF asynchronous circuits' design, simulation, VHDL, Signal Transition Graph (STG)
43Michael Münch, Manfred Glesner, Norbert Wehn An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling
43Peter A. Walker, Sumit Ghosh On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics
43Venkatram Krishnaswamy, Prithviraj Banerjee Actor Based Parallel VHDL Simulation Using Time Warp. Search on Bibsonomy Workshop on Parallel and Distributed Simulation The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VHDL, Time Warp, Parallel Discrete Event Simulation
43Ali Assi, Bozena Kaminska Modeling of communication protocols in VHDL. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards
43Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
41Allan H. Anderson, Gary A. Shaw Executable Requirements and Specifications. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
40Ernst Christen, Kenneth Bakalar VHDL 1076.1 - analog and mixed signal extensions to VHDL. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
40Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos Reasoning about VHDL and VHDL-AMS using Denotational Semantics. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF mixed-signal simulation, Language design, Language semantics, VHDL-AMS
40Douglas J. Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. Search on Bibsonomy DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VHDL
38Saeid Moslehpour, Chandrasekhar Puliroju, Christopher L. Spivey Simulating VHDL in PSpice Software. Search on Bibsonomy SCSS (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38David M. Kunzman, Terry Wilmarth, Laxmikant V. Kalé Parallel VHDL simulation. Search on Bibsonomy Winter Simulation Conference The full citation details ... 2005 DBLP  BibTeX  RDF
38Tom Fitzpatric System Verilog for VHDL Users. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Charles Hymans Design and Implementation of an Abstract Interpreter for VHDL. Search on Bibsonomy CHARME The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Charles Hymans Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation. Search on Bibsonomy SAS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Sara Blanc, Joaquin Gracia, Pedro J. Gil A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Joaquin Gracia, Daniel Gil, Juan Carlos Baraza, Pedro J. Gil Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture. Search on Bibsonomy PRDC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Yanbing Li, Miriam Leeser HML, a novel hardware description language and its translation to VHDL. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno Fast Hardware-Software Co-simulation Using VHDL Models. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Cristina Barna, Wolfgang Rosenstiel Object-Oriented Reuse Methodology for VHDL. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto Symbolic Functional Vector Generation for VHDL Specifications. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Peter J. Ashenden, Philip A. Wilsey, Dale E. Martin SUAVE: Extending VHDL to Improve Data Modeling Support. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Kwang-Il Park, Kyu Ho Park Event suppression by optimizing VHDL programs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Tom J. Kazmierski A Formal Description of VHDL-AMS Analogue Systems. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Peter J. Andersen, Philip A. Wilsey A Comparison of Alternative Extensions for Data Modeling in VHDL. Search on Bibsonomy HICSS (3) The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Chie Dou Integration of SDL and VHDL for HW/SW Codesign of Communication Systems. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
38Thomas Egolf, M. Pettigrew, James Debardelaben, R. Hezar, Shahram Famorzadeh, A. Kavipurapu, Moinul H. Khan, Lan-Rong Dung, K. Balemarthy, N. Desai, Vijay K. Madisetti VHDL-based rapid system prototyping. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
38Costas Courcoubetis, Werner Damm, Bernhard Josko Verification of timing Properties of VHDL. Search on Bibsonomy CAV The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
38Mani B. Srivastava, Robert W. Brodersen Using VHDL for High-Level, Mixed-Mode System Simulation. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
38John C. Willis, Daniel P. Siewiorek Optimizing VHDL Compilation for Parallel Simulation. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
38Paul J. Menchini A Minimalist Approach to VHDL Logic Modeling. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
38James Armstrong, Chang Cho, Sandeep Shah, Chakravarthy Kosaraju The VHDL Validation Suite. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
38Mart Altmäe MINT: a VHDL simulation system. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
38Paul R. Jordan, Ronald D. Williams COMP: A VHDL Composition System. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
38Joseph Lis, Daniel Gajski VHDL Synthesis Using Structured Modeling. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
38Jayaram Bhasker An algorithm for microcode compaction of VHDL behavioral descriptions. Search on Bibsonomy MICRO The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
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