The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Publications at "VLSI Design"( http://dblp.L3S.de/Venues/VLSI_Design )

URL (DBLP): http://dblp.uni-trier.de/db/conf/vlsid

Publication years (Num. hits)
1992 (82) 1993 (82) 1994 (89) 1995 (84) 1996 (102) 1997 (112) 1998 (312) 1999 (166) 2000 (152) 2001 (203) 2002 (197) 2003 (98) 2004 (176) 2005 (160) 2006 (168) 2007 (188) 2008 (158) 2009 (114) 2010 (100) 2011 (84) 2012 (128) 2013 (103) 2014 (134) 2015 (112) 2016 (144) 2017 (76) 2018 (97)
Publication types (Num. hits)
article(718) inproceedings(2878) proceedings(25)
Venues (Conferences, Journals, ...)
VLSI Design(3621)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 2039 occurrences of 970 keywords

Results
Found 3621 publication records. Showing 3621 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Chuandong Chen, Rongshan Wei, Shaohao Wang, Wei Hu Novel Verification Method for Timing Optimization Based on DPSO. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ioannis Intzes, Hongying Meng, John Paul Cosmas High Data Rate FinFET On-Off Keying Transmitter for Wireless Capsule Endoscopy. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mozammel H. A. Khan, Jacqueline E. Rice First Steps in Creating Online Testable Reversible Sequential Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shailendra Kumar Tripathi, Mohd. Samar Ansari, Amit M. Joshi Carbon Nanotubes-Based Digitally Programmable Current Follower. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mohamed Chentouf, Zine El Abidine Alaoui Ismaili A Novel Net Weighting Algorithm for Power and Timing-Driven Placement. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yin Li, Yu Zhang 0031, Xiaoli Guo Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Latika Desai, Suresh Mali Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Pragya Maheshwari, Sadhu Pavan Kumar, Mukesh Deharia, Nandakumar Nambath, Shalabh Gupta A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Felipe Mendes, Tiago Curtinhas, Duarte L. Oliveira, Higor A. Delsoto, Lester de Abreu Faria A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Bhuvana B. P., V. S. Kanchana Bhaaskaran Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, Prabhat Mishra Hardware Trojan Detection Using ATPG and Model Checking. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Abhishek Srivastava, Maryam Shojaei Baghini 0.36 nJ/bit MedRadio Band OOK Transmitter for Wearable Healthcare Applications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Linga Reddy Cenkeramaddi Feedback Biasing Based Adjustable Gain Ultrasound Preamplifier for CMUTs in 45nm CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Hari Shanker Gupta, Pranoy Datta, Maryam Shojaei Baghini, A. S. Kiran Kumar, Dinesh Kumar Sharma Low Power Configurable Readout Integrated Circuit for Infrared Detector. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sai Aparna Aketi, Joycee Mekie, Hemal Shah Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sourav Ghosh, Hafizur Rahaman, Chandan Giri Optimized Concurrent Testing of Digital Microfluidic Biochips. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sowmya Sankaranarayanan, Kulkarni Chaitali Vinod, Aswanth Sreekumar, Tonse Laxminidhi, Vipul Singhal, Rajat Chauhan Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Diego James, Abishek T. Kunnath, A. Purushothaman, Bibhu Datta Sahoo Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mayuran Sivanesan, Anupam Chattopadhyay, Bajaj Ronak Accelerating Hash Computations Through Efficient Instruction-Set Customisation. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mohammad Gh. Alfailakawi, Imtiaz Ahmad, Sarah Elghandour Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti SHIRT (Self Healing Intelligent Real Time) Scheduling for Secure Embedded Task Processing. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sumanta Pyne Rescheduling of Power Gating Instructions for Reduction of In-rush Current. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nan Zheng, Pinaki Mazumder A Low-Power Circuit for Adaptive Dynamic Programming. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sudeep Pasricha Overcoming Energy and Reliability Challenges for IoT and Mobile Devices with Data Analytics. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ankit Jindal, Binod Kumar 0001, Kanad Basu, Masahiro Fujita ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Rolf Arne Kjellby, Thor Eirik Johnsrud, Svein Erik Loetveit, Linga Reddy Cenkeramaddi, Mohamed Hamid, Baltasar Beferull-Lozano Self-Powered IoT Device for Indoor Applications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vulisi Narendra Kumar, Gayadhar Panda FPGA Implementation of Power Management Algorithm for Wind Energy Storage System with Kalman Filter MPPT Technique. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Avishek Choudhury, Biplab K. Sikdar Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sucheth S. Kuncham, Manasa Gadiyar, Sushmitha Din K., Kiran Kumar Lad, Tonse Laxminidhi A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Narendra Nath Ghosh, Prakash Kumar Lenka, SriHarsa Vardan G, Ashudeb Dutta A 0.6 mW 1.6 dB Noise Figure Inductorless Shunt Feedback Wideband LNA With Gm Enhancement and Current Reuse in 65 nm CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Arpan Chakraborty, Piyali Datta, Rajat Kumar Pal Design Optimization at the Fluid-Level Synthesis for Safe and Low-Cost Droplet-Based Microfluidic Biochips. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1John Jose, Abhijit Das 0002 An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sneh Saurabh, Priyanka Mittal A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1M. Mohamed Asan Basiri, Sk. Noor Mahammad An Efficient VLSI Architecture for Convolution Based DWT Using MAC. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Subhash J. Patel, Rajesh A. Thakker Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shi Jin, Krishnendu Chakrabarty Data-Driven Resiliency Solutions for Boards and Systems. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Amrita Roy Chowdhury, Parameswaran Ramanathan PPU: Privacy-Aware Purchasing Unit for Residential Customers in Smart Electric Grids. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya Test-Time Reduction for Power-Aware 3D-SoC. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha, Mayank Shrivastava On the ESD Reliability Issues in Carbon Electronics: Graphene and Carbon Nano Tubes. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Preyesh Dalmia, Vikas, Abhinav Parashar, Akshi Tomar, Neeta Pandey Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Kamal Chapagai, Pydi Bahubalindruni, Nishtha 2nd Order Sallen Key Switched Capacitor LPF with N-type Transistors. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tarun Vatwani, Arko Dutt, Debjyoti Bhattacharjee, Anupam Chattopadhyay Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Punith R. Surkanti, Annajirao Garimella, Paul M. Furth Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dharshak B. S., Rahul M. Rao A High Performance Gated Voltage Level Translator with Integrated Multiplexer. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sarani Bhattacharya, Shivam Bhasin, Debdeep Mukhopadhyay Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor Towards Near Data Processing of Convolutional Neural Networks. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ravikumar Selvam, Akhilesh Tyagi Power Side Channel Resistance of RNS Secure Logic. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Antonio Anastasio Bruto da Costa, Shriya Dharade, Sudipa Mandal, Pallab Dasgupta AMS-Miner: Mining AMS Assertions Using Interval Arithmetic. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sudipa Mandal, Aritra Hazra, Pallab Dasgupta, Chunduri Rama Mohan Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar 0001 CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Preeti Ranjan Panda, Namita Sharma 0001, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh Exploration of Loop Unroll Factors in High Level Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vinay Kumar, Ravindra kumar Shrivatava, Madhav Mansukh Padaliya A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T SRAM in FinFET Technology. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ashish Kumar, G. S. Visweswaran A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy Design Space Exploration of an Execution-Driven Functional Simulation Methodology. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nupur Jain, Mansi Singh, Biswajit Mishra Image Compression Using 2D-Discrete Wavelet Transform on a Light Weight Reconfigurable Hardware. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Manikandan R. R., Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sarit Chakraborty, Chandan Das, Susanta Chakraborty Securing Module-Less Synthesis on Cyberphysical Digital Microfluidic Biochips from Malicious Intrusions. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Xiaobang Liu, Ranga Vemuri Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1James Thesing, Dhireesha Kudithipudi Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ravi Krishnan Unni, Vijayanand P., Y. Dilip FPGA Implementation of an Improved Watchdog Timer for Safety-Critical Applications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ramakrishna Vaikuntapu, Lava Bhargava, Vineet Sahula Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Gregory Chang, Shovan Maity, Baibhab Chatterjee, Shreyas Sen Design Considerations of a Sub-50 Mu-W Receiver Front-end for Implantable Devices in MedRadio Band. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mannem Naga Sasikanth, Tarun Kanti Bhattacharyya A High Efficiency Body Injected Differential Power Amplifier at 2.4GHz for Low Power Applications. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Uma Mukund Kulkarni, Chetan Parikh, Subhajit Sen A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Arindam Sinharay, Pranab Roy, Hafizur Rahaman Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ankur Shukla, Rahul M. Rao, James D. Warnock Impact of Device Aging on Early Mode Failures in Pulsed Latches. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar Lightweight Forth Programmable NoCs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mahesh S. Murty, Rahul Shrestha Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Richa Chakravarty, Dipankar Saha, Santanu Mahapatra New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji Towards Single Pin Scan for Extremely Low Pin Count Test. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor DPFair Scheduling with Slowdown and Suspension. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Khyamling Parane, Basavaraj Talawar, Prabhu Prasad B. M. YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mohd Tasleem Khan, Shaik Rafi Ahamed Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nitin Bansal, Saurabh Kumar Singh, Hemant Shukla, Madhvi Sharma A 0.29ps FOM Fast Transient any Cap Stable LVR in 28FDSOI. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Anjali Gopinath, Ravi Kumar Adusumalli, Rohit Ranganathan, Arya S. Pseudo-Continuous Output Switched-Capacitor Amplifier for Rail-to-Rail Current Sensing Application. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nitin Bansal, Rahul Gupta An NMOS Low Drop-out Voltage Regulator with -17dB Wide-Band Power Supply Rejection for SerDes in 22FDX. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ayan Palchaudhuri, Anindya Sundar Dhar High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vikas Rana CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Qadeer Ahmad Khan, Seong Joong Kim, Pavan Kumar Hanumolu Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Manish Gupta, Abhinav Kranti Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ashwani Kumar, Shubham Sahay, Manan Suri Switching-Time Dependent PUF Using STT-MRAM. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Joycee Mekie, Prashansa Mukim, Kimaya Kale Impact of Variations on Synchronizer Performance: An Experimental Study. Search on Bibsonomy VLSI Design The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ting-Li Chu, Sin-Hong Yu, Chorng-Sii Hwang Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability". Search on Bibsonomy VLSI Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yu Wang, Jian Chen 0004, Chien-In Henry Chen Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor. Search on Bibsonomy VLSI Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiaokun Yang, Nansong Wu, Jean H. Andrian Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure. Search on Bibsonomy VLSI Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #100 of 3621 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license