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Publications at "VLSI Design"( http://dblp.L3S.de/Venues/VLSI_Design )

URL (DBLP): http://dblp.uni-trier.de/db/conf/vlsid

Publication years (Num. hits)
1992 (82) 1993 (82) 1994 (89) 1995 (84) 1996 (102) 1997 (112) 1998 (312) 1999 (166) 2000 (152) 2001 (203) 2002 (197) 2003 (98) 2004 (176) 2005 (160) 2006 (168) 2007 (188) 2008 (158) 2009 (114) 2010 (100) 2011 (84) 2012 (128) 2013 (103) 2014 (134) 2015 (112) 2016 (144) 2017 (76) 2018 (98) 2019 (112)
Publication types (Num. hits)
article(718) inproceedings(2989) proceedings(27)
Venues (Conferences, Journals, ...)
VLSI Design(3734)
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Found 3734 publication records. Showing 3734 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta 0001 Design and Implementation of Threshold Logic Functions Using Memristors. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Harshal Chapade, Rajesh Zele On-chip RF to DC Power Converter for Bio-Medical Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sanjay Vidhyadharan, Ramakant Ramakant, Abhay S. V, A. Krishna Shyam, Mohit P. Hirpara, Surya S. Dan An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Somdip Dey, Enrique Zaragoza Guajardo, Basireddy Karunakar Reddy, Xiaohang Wang, Amit Kumar Singh, Klaus D. McDonald-Maier EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ramakant Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary, Surya S. Dan Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shih-Chang Hung, Nick Iliev, Balajee Vamanan, Amit Ranjan Trivedi Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined Networking. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dipika Deb, John Jose, Maurizio Palesi Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesh Karri Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Manoj Kumar Sharma, Umesh Chandra Lohani, Vivek Parmar, Manan Suri Design of an Optimized CMOS ELM Accelerator. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rajat Sadhukhan, Nilanjan Datta, Debdeep Mukhopadhyay A Machine Learning Based Approach to Predict Power Efficiency of S-Boxes. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rahul Shrestha, Pooja Bansal, Srikant Srinivasan High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ankush Srivastava, Prokash Ghosh An Efficient Memory Zeroization Technique Under Side-Channel Attacks. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1T. Pravinraj, Rajendra Patrikar Modeling, Fabrication and Investigation of Mixing in Low-Cost Passive PDMS Micromixers. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri Hardware Trojan Detection by Stimulating Transitions in Rare Nets. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jinti Hazarika, Mohd Tasleem Khan, Shaik Rafi Ahamed Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sana Mujeeb, Krishna Kanth Gowri Avalur A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI Robustness. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Debdut Biswas, Tarun Kanti Bhattacharyya A Model of Spurs for Delta-Sigma Fractional PLLs. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Richa Agrawal, Mike Borowczak, Ranga Vemuri A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vipul Jain, Saurabh Kumar Gupta, Vishal Khatri, Gaurab Banerjee A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad, Ravindra Shrivastava Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jinn-Pean Lin, Jing Lu 0003, Jian Cai 0001, Aviral Shrivastava Efficient Heap Data Management on Software Managed Manycore Architectures. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vaibhav Agarwal, Sneh Saurabh Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rajeswari Devadoss, Kolin Paul, M. Balakrishnan Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shukla Banik, Suchismita Roy, Bibhash Sen Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Karthik Narayanan, Vinayak Honkote, Dibyendu Ghosh, Swamy Baldev Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Antroy Roy Chowdhury, Nijwm Wary, Pradip Mandal Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019 Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  BibTeX  RDF
1Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta Synthesizing Performance-Aware (m, k)-Firm Control Execution Patterns Under Dropped Samples. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pramod Kumar Bharti, Neelam Surana, Joycee Mekie Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ghanshyam Bairwa, Souvik Mandal, Tatavarthy Venkat Nikhil, Bodhisatwa Mazumdar Linear Approximation and Differential Attacks on Logic Locking Techniques. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Manish Gupta, Abhinav Kranti Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kundan Kumar, Raghunath K. P, Akshay Muraleedharan, Javed S. Gaggatur, Gaurab Banerjee A 75-µW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jay Pathak, Anand D. Darji Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Bikram Paul, Apratim Khobragade, Soumith Javvaji Sai, Sushree Sila P. Goswami, Sunil Dutt, Gaurav Trivedi Design and Implementation of Low-Power High-throughput PRNGs for Security Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Binod Kumar 0001, Masahiro Fujita, Virendra Singh A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vasudevan M. S, Santosh Biswas, Aryabartta Sahu RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Koushik Bharadwaj, Ashok Ray, Sushanta Bordoloi, Gaurav Trivedi Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Arjun Singh Chauhan, Vineet Sahula, Atanendu S. Mandal Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shixiong Jiang, Sheena Ratnam Priya, Naveena Elango, James Clay, Ramalingam Sridhar An Energy Efficient In-Memory Computing Machine Learning Classifier Scheme. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Navin Singhal, M. Santosh, S. C. Bose Reconfigurable Digital Logic Gate Based on Neuromorphic Approach. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Varun Kumar Dwivedi, Meenakshi Didharia, Madhvi Sharma, Manoj Kumar Sharma Comparative Study of Analog Matching Structures in 28FDSOI. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal Two-Pattern ∆IDDQ Test for Recycled IC Detection. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abhishek Srivastava, Maryam Shojaei Baghini Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical Receivers. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Lavanya Maddisetti, J. V. R. Ravindra Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rahul Pathak, Raghavendra Kongari, Shankar Joshi Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. S, Sujata K, Nalini C. Iyer Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amr Sayed-Ahmed, Jawad Haj-Yahya, Anupam Chattopadhyay SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gaurav Mishra, Urvi Ahluwalia, Karan Praharaj, Shreyangi Prasad RF and RFID Based Object Identification and Navigation System for the Visually Impaired. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tapalina Banerjee, Sudip Poddar, Sarmishtha Ghoshal, Bhargab B. Bhattacharya Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tathagato Bose, Kamalika Datta, Indranil Sengupta 0001 Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yudai Sakamoto, Shigeru Yamashita Reducing the Overhead of Stochastic Number Generators Without Increasing Error. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jaidev Shenoy, Kelly A. Ockunzzi, Virendra Singh, Kushal Kamal On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sidhartha Sankar Rout, Kanad Basu, Sujay Deb Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma Large Dynamic Range Readout Integrated Circuit for Infrared Detectors. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Arijit Nath, Hemangee K. Kapoor Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sanket Thakkar, Biswajit Mishra Ultra Low Power Digital Front-End for Single Lead ECG Acquisition. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Subhash Jagadishchandra Patel, Rajesh A. Thakker Parasitic-Aware Automatic Analog CMOS Circuit Design Environment. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jayaraj U. Kidav, N. M. Sivamangai, M. P. Pillai, Sreejeesh S. G Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mustafa M. Shihab, Vishwani Agrawal Energy Efficient Power Distribution on Many-Core SoC. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Anant Rungta, Kavindra Kandpal IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rohit Rothe, Rajesh Zele Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer Architecture. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Satyabrata Dash, Sukanta Dey, Anish Augustine, Sankar Dhar, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yooseong Kim, Mohammad Khayatian, Aviral Shrivastava WCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad Memories. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maruthi Gillela, Vaclav Prenosil, Venkat Reddy Ginjala Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vaishali Dhare, Usha Mehta A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora 0001 MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Swagata Mandal, Sreetama Sarkar, Ming Ming Wong, Anupam Chattopadhyay, Amlan Chakrabarti Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Arijit Banerjee 0002, Benton H. Calhoun A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Indu Yadav, Ashish Joshi, Ettore Ruscino, Valentino Liberali, Attilio Andreazza, Hitesh Shrimali Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shubham Negi, Ashis Maity, Amit Patra, Mrigank Sharad Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic Panel. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode-Based Array. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Timothy Dee, Ian Richardson, Akhilesh Tyagi Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric Authentication. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abirmoya Santra, Qadeer A. Khan A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shubhanshu Gupta, Joycee Mekie Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Japesh Vohra, Hande Vinayak Gopal Ultra Low Energy Reduced Switching DAC for SAR ADC. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers Applying Modified Householder Transform to Kalman Filter. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Rakesh Das, Anupam Chattopadhyay, Hafizur Rahaman Optimizing Quantum Circuits for Modular Exponentiation. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ajay Homkar, Satish Patil, Lukman Rahumathulla, Raj Pawate, Sachin Ghanekar Extending STL BASOPs Used in 3GPP Codecs to Leverage Features of Modern DSP Architectures. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy Multidimensional Grid Aware Address Prediction for GPGPU. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Martin Geier, Tobias Burghart, Martin Hackl, Samarjit Chakraborty In Situ Latency Monitoring for Heterogeneous Real-Time Systems. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kiran Gopal, Avanish K Delay Skew Reduction in IO Glitch Filter. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Prajwal Prajwal Sharma, Prashanthi K, Vinay Chandrasekhar, Krishna Nagaraja, Vikas Vahiyal, Madhav Rao Design and Analysis of a Minimally Invasive and ECG Controlled Ventricular Assistive Device. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Lalit Dani, Neeraj Mishra, Bulusu Anand MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ayan Palchaudhuri, Anindya Sundar Dhar VLSI Architectures for Jacobi Symbol Computation. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Maneesh Kumar Pandey, Mohit Goyal, Parul Sharma, Rohit Sharma Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tripti Nirmalkar, Deepti Kanoujia, Kshitiz Varma Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature. Search on Bibsonomy VLSI Design The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
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