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Publication years (Num. hits)
1980-1985 (15) 1986-1988 (22) 1989-1991 (18) 1992-1993 (16) 1994 (17) 1995 (26) 1996 (16) 1997 (23) 1998 (20) 1999 (36) 2000 (25) 2001 (22) 2002 (28) 2003 (35) 2004 (34) 2005 (57) 2006 (64) 2007 (47) 2008 (51) 2009 (25) 2010 (28) 2011 (27) 2012 (34) 2013 (32) 2014 (26) 2015 (29) 2016 (26) 2017 (25) 2018 (28) 2019 (14)
Publication types (Num. hits)
article(357) book(1) incollection(1) inproceedings(504) phdthesis(3)
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Found 866 publication records. Showing 866 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
54Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele A flexible VLSI architecture for variable block size segment matching with luminance correction. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards
42Mario Kovac, N. Ranganathan JAGUAR: a high speed VLSI chip for JPEG image compression standard. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
42Shuenn-Yuh Lee, Chia-Chyang Chen VLSI implementation of programmable FFT architectures for OFDM communication system. Search on Bibsonomy IWCMC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FFT processor, low power, VLSI architecture
41Chien-Min Ou, Huang-Chun Roan, Wen-Jyi Hwang Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC. Search on Bibsonomy PSIVT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Fractional motion estimation, H.264 standard, Video coding, VLSI architecture
39Jinsang Kim, Tom Chen A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. Search on Bibsonomy CAMP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF image sequence segmentation, edge fusion, VLSI edge fusion architecture, segmentation, image sequences, image sequences, VLSI architecture, complexity analysis, gray level
36Shuenn-Yuh Lee, Chia-Chyang Chen, Shyh-Chyang Lee, Chih-Jen Cheng A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36S. Muller A new programmable VLSI architecture for histogram and statistics computation in different windows. Search on Bibsonomy ICIP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF programmable VLSI architecture, histogram computation, grey-scale histogram, image preprocessing methods, inhomogeneous illumination elimination, simple increment operations, histogrammer, window handling, arithmetic unit configuration, memory configuration, equalisation, simulation, image segmentation, VLSI, segmentation, data compression, data compression, statistics, image enhancement, image enhancement, texture analysis, image texture, digital signal processing chips, CMOS technology, binary images, CMOS digital integrated circuits, co-occurrence-matrix, statistics computation
35Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation
35N. Ranganathan, K. B. Doreswamy A systolic algorithm and architecture for image thinning. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
35Jin Jie, Chi-Ying Tsui, Wai Ho Mow A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. Search on Bibsonomy KES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, Te-Jung Lo VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications. Search on Bibsonomy ISCAS (5) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF shape-adaptive, boundary extension, discrete wavelet transform, VLSI architecture
34John A. Canaris A VLSI architecture for the real time computation of discrete trigonometric transforms. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF discrete trigonometric transforms, Goertzel's algorithm, Discrete cosine transform, VLSI architecture
32S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri A VLSI chip for image compression using variable block size segmentation. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques
32Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011 A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform". Search on Bibsonomy IEEE Trans. Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian VLSI decoder architecture for embedded zerotree wavelet algorithm. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Decision feedback equalizer, reusable VLSI implementation, FIR filter, QAM
31Gauthier Lafruit, Francky Catthoor, Jan Cornelis 0001, Hugo De Man An efficient VLSI architecture for 2-D wavelet image coding with novel image scan. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Kai He, Gert Cauwenberghs An area-efficient analog VLSI architecture for state-parallel Viterbi decoding. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Gert Cauwenberghs Bit-serial bidirectional A/D/A conversio. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
30Chao Wang, Wu Zhilin, Peng Cao 0002, Li Jie An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform. Search on Bibsonomy ICME The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Mahdi Shabany, P. Glenn Gulak Scalable VLSI architecture for K-best lattice decoders. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Isidoro Urriza, José Ignacio Artigas, José I. García-Nicolás, Luis Angel Barragan, Denis Navarro VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF DWT, VLSI architectures, Medical Image compression
27Fariborz Sobhanmanesh, Saeid Nooshabadi VLSI architecture for 4×4 16-QAM V-BLAST decoder. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder. Search on Bibsonomy ISCAS (5) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Byung Cheol Song, Kang Wook Chun Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Bok-Gue Park, Koon-Shik Cho, Jun Dong Cho Low Power VLSI Architecture of Viterbi Scorer for HMM-Based Isolated Word Recognition. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Viterbi Scoring, Low-Power, HMM, Speech Recognition
27Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Chien-Yu Chen 0001, Zhong-Lan Yang, Tu-Chih Wang, Liang-Gee Chen A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF wavelet, JPEG 2000, DSP architecture
27Wen-Shiaw Peng, Chen-Yi Lee An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform. Search on Bibsonomy ICIP (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese A VLSI Architecture for Modeling Intersegmental Coordination. Search on Bibsonomy ARVLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
27Cauligi S. Raghavendra HMESH: A VLSI Architecture for Parallel Processing. Search on Bibsonomy CONPAR The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
27Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. Search on Bibsonomy EUROMICRO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Chengjun Zhang, Chunyan Wang 0004, M. Omair Ahmad A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Y.-J. Wang, C.-C. Cheng, Tian-Sheuan Chang A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Dajiang Zhou, Peilin Liu A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Safar Hatami, Shervin Sharifi, Mahmoud Kamarei, Hossein Ahmadi Real-time image compression based on wavelet vector quantization, algorithm and VLSI architecture. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Leibo Liu, Xuejin Wang, Hongying Meng, Li Zhang 0023, Zhihua Wang, Hongyi Chen A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Jaehee You, Sang Uk Lee High Throughput, Scalable VLSI Architecture for Block Matching Motion Estimation. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
26O. Vermesan A Modular VLSI Architecture for Neural Networks Implementation. Search on Bibsonomy IWANN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
26Asmar A. Khan, Shahid Masud Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion. Search on Bibsonomy PSIVT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Display resolution conversion, QCIF, VGA, FPGA, VLSI architecture, Image-scaling
26Yang Sun, Joseph R. Cavallaro High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF mimo detection, VLSI architecture, ASIC design
26Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Motion estimation, Video coding, H.264/AVC, VLSI architecture
26Ibrahim Saeed Koko, Herman Agustiawan High-Speed and Power Efficient Lifting-Based VLSI Architecture for Two-Dimesional Discrete Wavelet Transform. Search on Bibsonomy Asia International Conference on Modelling and Simulation The full citation details ... 2008 DBLP  DOI  BibTeX  RDF pipelined, discrete wavelet transform, VLSI architecture, high-speed, lifting scheme
26Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fast intra prediction mode decision, H.264, VLSI architecture
26Junhao Zheng, Lei Deng, Peng Zhang, Don Xie An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF motion compensation, VLSI architecture, AVS
26Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF B-spline factorization, discrete wavelet transform, VLSI architecture
26Y.-K. Lai, L.-G. Chen, T.-H. Tsai, P.-C. Wu A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation. Search on Bibsonomy ICIP (2) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF flexible high-throughput VLSI architecture, 2D data-reuse, full-search motion estimation, data-interlacing architecture, one-dimensional processing element array, data-interlacing shift-register arrays, external memory accesses, pin counts, search ranges, pixel rates, VLSI, block sizes, full-search block-matching algorithm
26Subarna Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri A VLSI architecture for cellular automata based parallel data compression. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parallel data compression, nongroup CA, VLSI, parallel architectures, data compression, cellular automata, cellular automata, VLSI architecture, state transition
26Meenakshisundaram Gopi, Swami Manohar A VLSI architecture for the computation of NURBS patches. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF NURBS patches, nonuniform rational B-spline, interactive modeling session, patch generation, complete hardware solution, VLSI, computational geometry, parallel architectures, computer graphics, geometric modeling, VLSI architecture, splines (mathematics), B-spline curves
26In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits
26Zhan Guo, Peter Nilsson Algorithm and implementation of the K-best sphere decoding for MIMO detection. Search on Bibsonomy IEEE Journal on Selected Areas in Communications The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Hai Bing Yin, Zhe Lei Xia, Xi Zhong Lou An Improved Three-Step Hierarchical Motion Estimation Algorithm and Its Cost-Effective VLSI Architecture. Search on Bibsonomy PCM The full citation details ... 2007 DBLP  DOI  BibTeX  RDF TSS, VLSI, Motion Estimation
24Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer Energy Efficient VLSI Architecture for Linear Turbo Equalizer. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF iterative equalizer, SISO, turbo, architecture, low-power, iterative decoder
24Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. Search on Bibsonomy ICNC (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. Search on Bibsonomy KES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Amjad Hajjar, Tom Chen VLSI Architecture for Real-Time Edge Linking. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF edge linking, VLSI, real-time image processing
24Chuan-Yu Cho, Shiang-Yang Huang, Jeng-Neng Hwang, Jia-Shung Wang An embedded merging scheme for VLSI implementation of H.264/AVC motion estimation modules. Search on Bibsonomy ICIP (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Kai Liu, Keyan Wang, Yunsong Li, Chengke Wu A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF line-based, lifting-based, VLSI, wavelet transforms
24Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. Search on Bibsonomy MMM (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm
24Keyan Wang, Chengke Wu, Kai Liu, Yunsong Li, Jechang Jeong Efficient Line-Based VLSI Architecture for 2-D Lifting DWT. Search on Bibsonomy ICIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Evangelos F. Stefatos, Tughrul Arslan An Efficient Fault-Tolerant VLSI Architecture Using Parallel Evolvable Hardware Technology. Search on Bibsonomy Evolvable Hardware The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Junhao Zheng, Di Wu 0022, Lei Deng, Don Xie, Wen Gao 0001 A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder. Search on Bibsonomy PCM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS
22Hai Bing Yin, Xi Zhong Lou, Zhe Lei Xia, Wen Gao 0001 An efficient VLSI architecture for rate disdortion optimization in AVS video encoder. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22N. Gupta A VLSI Architecture for Image Registration in Real Time. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Zhan Guo, Peter Nilsson A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF square root algorithm, VLSI, wireless LAN, ASIC, MIMO, fixed-point, 3G, HSDPA, CORDIC, BLAST
22Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Cao Wei, Mao Zhi Gang A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Chengjun Zhang, Chunyan Wang 0004, M. Omair Ahmad A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Qionghai Dai, Xinjian Chen, Chuang Lin A novel VLSI architecture for multidimensional discrete wavelet transform. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22J. D. Kranthi Kumar, Shri K. V. Srinivasan A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Bing-Fei Wu, Chung-Fu Lin A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Swee Yeow Yap, John V. McCanny A VLSI Architecture for Advanced Video Coding Motion Estimation. Search on Bibsonomy ASAP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Yeong-Kang Lai, Yu-Chuan Shu VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
22Adel-Omar Dahmane, Daniel Massicotte, Leszek Szczecinski A VLSI architecture of a piecewise RBF decision feedback channel equalizer. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
22Chu Yu, Sao-Jie Chen Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. Search on Bibsonomy ISCAS (3) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
22Jen-Shiun Chiang, Jian-Kao Chen An efficient VLSI architecture for RSA public-key cryptosystem. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
22Amit Kumar Gupta, Saeid Nooshabadi, David Taubman, Michael Dyer Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
21Bing-Fei Wu, Hsin-Yuan Peng, Tung-Lung Yu Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
21Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
21Sungchan Park, Chao Chen, Hong Jeong VLSI Architecture for MRF Based Stereo Matching. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
21Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
21Andreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
21Jin Lee, Sin-Chong Park, Sungchung Park A pipelined VLSI architecture for a list sphere decoder. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
21P. John Paul, P. N. Girija A Novel VLSI Architecture for Image Compression. Search on Bibsonomy ISM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FHT, FCT, FST, Hybrid Transform, VLSI, FFT
21Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu VLSI architecture design for a fast parallel label assignment in binary image. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
21Minho Kim, Ingu Hwang, Soo-Ik Chae A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
21Evangelos F. Stefatos, Wei Han 0001, Tughrul Arslan, Robert Thomson 0003 Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
21Ashis Kumar Mal, Anindya Sundar Dhar Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
21Lei Deng, Ming-Zeng Hu, Zhenzhou Ji An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile. Search on Bibsonomy PCM (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
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