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1960-1977 (15) 1979-1991 (16) 1992-1994 (55) 1995 (56) 1996 (38) 1997 (39) 1998 (37) 1999 (32) 2000 (33) 2001 (40) 2002 (50) 2003 (51) 2004 (57) 2005 (48) 2006 (51) 2007 (53) 2008 (36) 2009 (42) 2010 (37) 2011 (31) 2012 (25) 2013 (34) 2014 (26) 2015 (31) 2016 (20) 2017 (23) 2018 (25)
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ASYNC(527) IEEE Trans. on CAD of Integrat...(20) DAC(19) IEEE Trans. Computers(18) ACSD(17) DATE(16) PATMOS(16) ICCAD(15) ICCD(15) IEEE Trans. VLSI Syst.(14) VLSI Design(13) Asian Test Symposium(10) ASP-DAC(10) DSD(10) ISVLSI(9) IOLTS(8) More (+10 of total 136)
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Found 1001 publication records. Showing 1001 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
71Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm Applying Asynchronous Circuits in Contactless Smart Cards. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
65Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor Security Evaluation of Asynchronous Circuits. Search on Bibsonomy CHES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis
62Mohsen Raji, Behnam Ghavami, Hossein Pedram Statistical static performance analysis of asynchronous circuits considering process variation. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
61Mehrdad Najibi, Kamran Saleh, Hossein Pedram Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF quasi-delay insensitive, standard-cell layout, asynchronous circuits
61G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF QDI Asynchronous circuits, Path Swapping (PS), Power analysis
58Yannick Monnet, Marc Renaudin, Régis Leveugle Asynchronous circuits transient faults sensitivity evaluation. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
58Frank te Beest, Kees van Berkel, Ad M. G. Peeters Adding Synchronous and LSSD Modes to Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF design for testability, asynchronous circuits, scan test, LSSD
58Ad M. G. Peeters, Kees van Berkel Single-rail handshake circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
57Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
57Rik van de Wiel High-level test evaluation of asynchronous circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes
56Eckhard Grass, S. Jones Asynchronous circuits based on multiple localised current-sensing completion detection. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
56Nitin Gupta, Doug A. Edwards Synthesis of Asynchronous Circuits Using Early Data Validity. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
55Kent L. Einspahr, Sharad C. Seth A switch-level test generation system for synchronous and asynchronous circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
54Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas New CMOS VLSI linear self-timed architectures. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
54Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald Delay Insensitive Encoding and Power Analysis: A Balancing Act. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
53Ding Lu, Carol Q. Tong High level fault modeling of asynchronous circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high level fault modeling, transitional fault models, stuck-at-false model, stuck-at-true model, fault diagnosis, logic testing, timing, asynchronous circuits, asynchronous circuits, signal transition graph, signal flow graphs, self-timed circuits
53Michael J. Liebelt, Cheng-Chew Lim A method for determining whether asynchronous circuits are self-checking. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
51Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Lilian Janin, Doug Edwards Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design. Search on Bibsonomy IV The full citation details ... 2005 DBLP  DOI  BibTeX  RDF program comprehension, asynchronous circuits, Software visualisation, coordinated views
51Martin Simlastík, Viera Stopjaková Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
51Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin Partial-scan delay fault testing of asynchronous circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
50Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
50Kees van Berkel, Ferry Huberts, Ad M. G. Peeters Stretching quasi delay insensitivity by means of extended isochronic forks. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits
50Frank te Beest, Ad M. G. Peeters, Kees van Berkel, Hans G. Kerkhoff Synchronous Full-Scan for Asynchronous Handshake Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF L1L2*, DFT, asynchronous circuits, scan design, LSSD
49Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
48Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Wendy Belluomini, Chris J. Myers Efficient Timing Analysis Algorithms for Timed State Space Exploration. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders
47Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
47Morteza Damavandpeyma, Siamak Mohammadi Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
46Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng Automatic synthesis of gate-level timed circuits with choice. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
46Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng Technology mapping of timed circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
46Amy Streich, Alex Kondratyev, Lief Sorensen Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ATPG, asynchronous circuits, stuck-at faults, partial scan
46Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. Search on Bibsonomy ISMVL The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
45Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks On-chip samplers for test and debug of asynchronous circuits. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Ajay Khoche, Erik Brunvand Critical hazard free test generation for asynchronous circuits. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm
45Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin Partial scan delay fault testing of asynchronous circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
44Garth Baulch, David Hemmendinger, Cherrice Traver Analyzing and verifying locally clocked circuits with the concurrency workbench. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
44Chantal Ykman-Couvreur, Bill Lin Efficient state assignment framework for asynchronous state graphs. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF state assignment framework, asynchronous state graphs, state graph level, complete state coding problem, circuit area, logic design, encoding, asynchronous circuits, asynchronous circuits, computation time, state assignment
44Radu Negulescu, Ad M. G. Peeters Verification of Speed-Dependences in Single-Rail Handshake Circuits. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF single-rail, isochronic forks, verification, timing, asynchronous circuits, progress, speed-independent circuits, process spaces, handshake circuits
44Cheoljoo Jeong, Steven M. Nowick Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Bao Liu Robust differential asynchronous nanoelectronic circuits. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
43Eric Keller Building Asynchronous Circuits with JBits. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva High-Level Asynchronous System Design Using the ACK Framework. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
42Jo C. Ebergen, Robert Berks Response Time Properties of Some Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF variable-delay model, performance analysis, Asynchronous circuits, response time, micropipeline
42Nikolai Starodoubtsev, Sergei Bystrov Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
42Jun Gu, Ruchir Puri Asynchronous circuit synthesis with Boolean satisfiability. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
42Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland Implementing Asynchronous Circuits on LUT Based FPGAs. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42John O'Leary, Geoffrey Brown Synchronous emulation of asynchronous circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
40Victor Khomenko, Maciej Koutny, Alexandre Yakovlev Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. Search on Bibsonomy ACSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits
40Chris J. Myers, Teresa H. Y. Meng Synthesis of timed asynchronous circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis Asynchronous circuit design on reconfigurable devices. Search on Bibsonomy SBCCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGAs, asynchronous circuits
39Frédéric Béal, Tomohiro Yoneda, Chris J. Myers Hazard Checking of Timed Asynchronous Circuits Revisited. Search on Bibsonomy ACSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Wendy Belluomini, Chris J. Myers, H. Peter Hofstee Verification of Delayed-Reset Domino Circuits Using ATACS. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Mark B. Josephs Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Dilip P. Vasudevan, Aristides Efthymiou A Partial Scan Based Test Generation for Asynchronous Circuits. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38J. Gong, Eddie M. C. Wong Verification of Asynchronous Circuits with Bounded Inertial Gate Delays. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Ganesh Gopalakrishnan, Venkatesh Akella High-level optimizations in compiling process descriptions to asynchronous circuits. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
38Nikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev Monotonic Circuits with Complete Acknowledgement. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Robert Berks, Radu Negulescu Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38Masashi Imai, Metehan Özcan, Takashi Nanya Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. Search on Bibsonomy ASYNC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Feng Shi, Yiorgos Makris Testing delay faults in asynchronous handshake circuits. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test generation, asynchronous circuits, delay faults, handshake circuits
37Menahem Lowy, Neal Butler, Rosanne Tinkler Low power VLSI sequential circuit architecture using critical race control. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF critical races, low-power VLSI circuits, asynchronous circuits
37Arash Saifhashemi, Hossein Pedram Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CHP, PLI, CSP, asynchronous circuits, channel, verilog
37Thomas Verdel, Yiorgos Makris Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy Fsimac: a fault simulator for asynchronous sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
36Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell Delay Insensitive Logic for RSFQ Superconductor Technology. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
35Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel Design of a High-Speed Asynchronous Turbo Decoder. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Mark B. Josephs An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Ivan E. Sutherland, Jon K. Lexau Designing Fast Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Per Arne Karlsen, Per Torstein Røine A Timing Verifier and Timing Profiler for Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Alexander H. Jackson, Andrew M. Tyrrell Asynchronous Embryonics. Search on Bibsonomy Evolvable Hardware The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Yu Zhou 0006, Danil Sokolov, Alexandre Yakovlev Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Alireza Kaviani Phase Alignment Using Asynchronous State Machines. Search on Bibsonomy ASYNC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Christos P. Sotiriou Implementing asynchronous circuits using a conventional EDA tool-flow. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF tool-flow, asynchronous, EDA
33Abdel Ejnioui FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Feng Shi, Yiorgos Makris Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Yannick Monnet, Marc Renaudin, Régis Leveugle Asynchronous Circuits Sensitivity to Fault Injection. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Metehan Özcan, Masashi Imai, Takashi Nanya Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Xiaohua Kong, Radu Negulescu Formal verification of pulse-mode asynchronous circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Josep Carmona, Jordi Cortadella, Enric Pastor A structural encoding technique for the synthesis of asynchronous circuits. Search on Bibsonomy ACSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Sung Tae Jung, Chris J. Myers Direct synthesis of timed asynchronous circuits. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff Verification of Bounded Delay Asynchronous Circuits with Timed Traces. Search on Bibsonomy AMAST The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Hon Fung Li, P. N. Lam A protocol extraction strategy for control point insertion in design for test of transition signaling circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF protocol extraction strategy, control point insertion, transition signaling circuits, hazard-free test, safe behaviors, gap detection, gap matching, single input pad, protocols, logic testing, design for testability, asynchronous circuits, asynchronous circuits, design for test, test length, area overhead
32Waleed K. Al-Assadi, Sindhu Kakarla Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 2009 DBLP  DOI  BibTeX  RDF NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)
32Song Peng, Rajit Manohar Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
32Werner Erhard, Andreas Reinsch, Torsten Schober First Steps towards a Reconfigurable Asynchronous System. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Petri nets, design methodology, asynchronous circuits, reconfigurable hardware
32Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin State-holding in Look-Up Tables: application to asynchronous logic. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Yannick Monnet, Marc Renaudin, Régis Leveugle Hardening Techniques against Transient Faults for Asynchronous Circuits. Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Lei Wang 0011, Zhiying Wang, Kui Dai An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings. Search on Bibsonomy CIT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31John Teifel, Rajit Manohar An Asynchronous Dataflow FPGA Architecture. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Asynchronous/synchronous operation, reconfigurable hardware, gate arrays, dataflow architectures
30Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev An Asynchronous Synthesis Toolset Using Verilog. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Matthew L. King, Kewal K. Saluja Testing Micropipelined Asynchronous Circuits. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Alex Kondratyev, Kelvin Lwin Design of Asynchronous Circuits Using Synchronous CAD Tools. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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