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1986-1990 (24) 1991-1993 (32) 1994 (29) 1995 (68) 1996 (61) 1997 (68) 1998 (53) 1999 (79) 2000 (66) 2001 (55) 2002 (106) 2003 (99) 2004 (115) 2005 (101) 2006 (108) 2007 (106) 2008 (106) 2009 (44) 2010-2015 (16) 2017 (1)
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article(413) incollection(1) inproceedings(923)
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Found 1337 publication records. Showing 1337 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
64Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek Evolution of synthetic RTL benchmark circuits with predefined testability. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF evolvable hardware, testability analysis, Benchmark circuit
61Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen Fanout fault analysis for digital logic circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
54Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout Generating synthetic benchmark circuits for evaluating CAD tools. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
47Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Search on Bibsonomy Evolvable Hardware The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng Incremental logic rectification. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general single-gate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach
37Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai Benchmark Circuits Improve the Quality of a Standard Cell Library. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Seok-Bum Ko, Jien-Chung Lo Efficient Decomposition Techniques for FPGAs. Search on Bibsonomy HiPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Youngmin Kim, Dusan Petranovic, Dennis Sylvester Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF capacitance increment, metal fill insertion, inter level dielectric thickness planarity, metal dummy, signal capacitance, electrical characteristic, signal dimensions, dummy shape, dummy dimensions, simple test patterns, benchmark circuits, weighting function
34Michael A. Riepe, Karem A. Sakallah Transistor placement for noncomplementary digital VLSI cell synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Cell Synthesis, Euler graphs, noncomplementary circuits, sequence pair optimization, transistor chaining, transistor placement, digital circuits, benchmark circuits
34Shantanu Dutt, Wenyong Deng VLSI circuit partitioning by cluster-removal using iterative improvement techniques. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ACM/SIGDA benchmark circuits, Fiduccia-Mattheyses algorithm, VLSI circuit partitioning, cluster-removal, iterative improvement techniques, look-ahead algorithm, partition quality, spectral partitioner MELO, VLSI, CAD
34Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel Cyclic stress tests for full scan circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
34Rajesh Nair, Dong Sam Ha VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
34Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò Reliability evaluation of combinational logic circuits by symbolic simulation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
34Pranav Ashar, Sharad Malik Fast functional simulation using branching programs. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
31Paul D. Kundarewich, Jonathan Rose Synthetic circuit generation using clustering and iteration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Paul D. Kundarewich, Jonathan Rose Synthetic circuit generation using clustering and iteration. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita Test sequence compaction for sequential circuits with reset states. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
30Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal Compaction-based test generation using state and fault information. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
30Elizabeth M. Rudnick, Janak H. Patel Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits
30Koji Yamazaki, Teruhiko Yamada An approach to diagnose logical faults in partially observable sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution
30Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal On test coverage of path delay faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
30Mark C. Hansen, John P. Hayes High-level test generation using physically-induced faults. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
30Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu Generation of tenacious tests for small gate delay faults in combinational circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
30Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck Deterministic test generation for non-classical faults on the gate level. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
30Debesh K. Das, Bhargab B. Bhattacharya Testable design of non-scan sequential circuits using extra logic. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
30Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey A simple technique for locating gate-level faults in combinational circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
30Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger Early evaluation for performance enhancement in phased logic. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Marc D. Riedel, Jehoshua Bruck The synthesis of cyclic combinational circuits. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF feedback, logic synthesis, cycles, combinational logic
30Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal Redundancy removal and test generation for circuits with non-Boolean primitives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
30Chuan-Yu Wang, Kaushik Roy 0001 COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF CMOS Digital Circuits, Reliability, Power Estimation
28Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne Design space exploration for field programmable compressor trees. Search on Bibsonomy CASES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF design space exploration (dse), field programmable compressor tree (fpct)
28Bin Zhang 0011, Wei-Shen Wang, Michael Orshansky FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes BenCGen: a digital circuit generation tool for benchmarks. Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF benchmarks, sat solvers, combinational equivalence checking
27Marvin Tom, David Leong, Guy G. Lemieux Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
27Seok-Bum Ko Area Minimization of Exclusive-OR Intensive Circuits in FPGAs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, XOR, ESOP
27Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng Covering conditions and algorithms for the synthesis of speed-independent circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
27Kwang-Ting Cheng Transition fault testing for sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
27Marie-Lise Flottes, Christian Landrault, A. Petitqueux Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
27Mukund Sivaraman, Andrzej J. Strojwas Diagnosis of parametric path delay faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
27Michel Renovell, P. Huc, Yves Bertrand Bridging fault coverage improvement by power supply control. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
27Mukund Sivaraman, Andrzej J. Strojwas A diagnosability metric for parametric path delay faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
27Khushro Shahookar, Pinaki Mazumder Genetic multiway partitioning. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
27Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges Statistical estimation of delay fault detectabilities and fault grading. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
27Ted Stanion, Carl Sechen Quasi-algebraic decompositions of switching functions. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF quasi-algebraic decompositions, algebraic product, binary Boolean operation, canonical manner, SSL testable, logic testing, testability, switching functions, switching functions, state assignment, minimisation of switching nets, benchmark circuits, circuit size
27Tomoo Inoue, Hironori Maeda, Hideo Fujiwara A scheduling problem in test generation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test generation schedule, testing cost, dominating probability, ISCAS'85 benchmark circuits, combinational logic circuit testing, scheduling, logic testing, probability, integrated circuit testing, combinational circuits, automatic testing, test-pattern generation, processing time, scheduling problem
27Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams On the decline of testing efficiency as fault coverage approaches 100%. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
27Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja An optimized testable architecture for finite state machines. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence
27Andrej Zemva, Franc Brglez Detectable perturbations: a paradigm for technology-specific multi-fault test generation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
27Eiji Harada, Janak H. Patel Overhead reduction techniques for hierarchical fault simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
27Yu Fang, Alexander Albicki Efficient testability enhancement for combinational circuit. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
27Sudhakar M. Reddy Testing-what's missing? An incomplete list of challenges. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testing area, quality guarantees, special-purpose procedures, integrated design and test, high-level failure models, program testing, computer testing, benchmark circuits, design cycle
27Shantanu Dutt, Wenyong Deng Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VLSI circuit partitioning, mincut, physical design/layout, Clusters, iterative-improvement
27Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Clock-delayed domino circuit, Fault simulation, crosstalk fault
27Ramesh C. Tekumalla, Premachandran R. Menon Identification of primitive faults in combinational and sequentialcircuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001 Extraction of functional regularity in datapath circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Masahiro Fujita Verification of Arithmetic Circuits by Comparing Two Similar Circuits. Search on Bibsonomy CAV The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
27Kent L. Einspahr, Sharad C. Seth A switch-level test generation system for synchronous and asynchronous circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
27Srimat T. Chakradhar, Steven G. Rothweiler Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
26Kazuo Iwama, Kensuke Hino, Hiroyuki Kurokawa, Sunao Sawada Random benchmark circuits with controlled attributes. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
24Mukund Sivaraman, Andrzej J. Strojwas Path delay fault diagnosis and coverage-a metric and an estimationtechnique. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Albrecht P. Stroele, Hans-Joachim Wunderlich Hardware-optimal test register insertion. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
24Tai-Chen Chen, Yao-Wen Chang Multilevel full-chip gridless routing considering optical proximity correction. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Luis Entrena-Arrontes, Kwang-Ting Cheng Combinational and sequential logic optimization by redundancy addition and removal. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
24Mihir R. Choudhury, Kartik Mohanram Reliability Analysis of Logic Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker 0001 On Reducing Circuit Malfunctions Caused by Soft Errors. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Wang-Dauh Tseng, Lung-Jen Lee Reduction of Power Dissipation during Scan Testing by Test Vector Ordering. Search on Bibsonomy MTV The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Lin Yuan, Gang Qu A combined gate replacement and input vector control approach for leakage current reduction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Amit Chowdhary, John P. Hayes Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic Structural analysis and generation of synthetic digital circuits with memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
24Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal Energy models for delay testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
24Anand Raghunathan, Srimat T. Chakradhar Acceleration techniques for dynamic vector compaction. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Dynamic equivalent and untestable fault analysis, Target fault switching, Support sets, Test compaction, Acceleration Techniques
21David Grant, Guy G. Lemieux Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. Search on Bibsonomy TRETS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Automated development tools, hardware-supporting software, testing, graph algorithms, design automation, place and route
21Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden ISPD placement contest updates and ISPD 2007 global routing contest. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
21David Grant, Scott Chin, Guy G. Lemieux Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
21Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung Exploration of heterogeneous reconfigurable architectures (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
21Seongmoon Wang A BIST TPG for Low Power Dissipation and High Fault Coverage. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
21Amit Chowdhary, John P. Hayes General technology mapping for field-programmable gate arrays based on lookup tables. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
21Michael D. Hutton, Jonathan Rose Equivalence classes of clone circuits for physical-design benchmarking. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
21Krishnendu Chakrabarty, Brian T. Murray Design of built-in test generator circuits using width compression. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
21Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli Logic synthesis for large pass transistor circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF logic synthesis, BDD, Pass transistor logic
21Gin Yee, Carl Sechen Clock-Delayed Domino for Adder and Combinational Logic Desig. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
21Albrecht P. Stroele, Hans-Joachim Wunderlich Test register insertion with minimum hardware cost. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test register insertion, BILBO, CBILBO, Built-in self-test
20Sumanth Amarchinta, Dhireesha Kudithipudi Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF charge-boosters, subthreshold design, biasing
20Mihir R. Choudhury, Kartik Mohanram Timing-driven optimization using lookahead logic circuits. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF logic synthesis, timing optimization, lookahead
20Anish Muttreja, Srivaths Ravi 0001, Niraj K. Jha Variability-Tolerant Register-Transfer Level Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
20Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta Event propagation for accurate circuit delay calculation using SAT. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Critical delay, event propagation, SAT
20Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001 Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta A Novel Approach to Domino Circuit Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula Power Virus Generation Using Behavioral Models of Circuits. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
20Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001 Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF detection latency, discrete event systems, ordered binary decision diagrams, fault detection and diagnosis
20Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
20Debasis Samanta, Ajit Pal Synthesis of Low Power High Performance Dual-VT PTL Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada Practical Fault Coverage of Supply Current Tests for Bipolar ICs. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura Timing optimization by replacing flip-flops to latches. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Srivathsan Krishnamohan, Nihar R. Mahapatra A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Geun Rae Cho, Tom Chen On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
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