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Found 1054 publication records. Showing 1054 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
101Hardy J. Pottinger, Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
91Abhijit Chatterjee, Jacob A. Abraham Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
91Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin A built-in self-test and self-diagnosis scheme for embedded SRAM. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
78Sying-Jyan Wang, Chen-Jung Wei Efficient built-in self-test algorithm for memory. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
78Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi Low-cost DC built-in self-test of linear analog circuits using checksums. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
78Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
78Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer Arithmetic built-in self test for high-level synthesis. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
76Ilker Hamzaoglu, Janak H. Patel Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
74K. Y. Ko, Mike W. T. Wong New built-in self-test technique based on addition/subtraction of selected node voltages. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF node voltages, built-in self test, built-in self-test, fault detection, fault location, analogue circuits
72Joan Carletta, Christos A. Papachristou Structural constraints for circular self-test paths. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
71Paul Chang, Brion L. Keller, Sarala Paliwal Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
68Chen-Huan Chiang, Sandeep K. Gupta BIST TPG for faults in system backplanes. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration
66Mehdi Ehsanian, Bozena Kaminska, Karim Arabi A new digital test approach for analog-to-digital converter testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
66Albrecht P. Stroele Signature analysis and aliasing for sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
66R. K. Sharma, Aditi Sood Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Faults. Search on Bibsonomy ICSAP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Defect-Per Million (DPM), Memory Built-in Self Test (MBIST), Microcoded MBIST, MUT (Memory Under Test), Built-In Self Test (BIST)
66Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak An improved output compaction technique for built-in self-test in VLSI circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
66Peter D. Hortensius, Robert D. McLeod, Howard C. Card Cellular Automata-Based Signature analysis for Built-in Self-Test. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF signature analysis properties, one-dimensional cellular automata, cyclic-group rules, CALBO, cellular automata-based logic block observation, BILBO, built-in block observation, logic testing, built-in self-test, built-in self test, LFSR, linear feedback shift register, finite automata, test pattern generation
65Diogo José Costa Alves, Edna Barros A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF LBIST, compressed test patterns, test, SoC, self-test
64Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis An efficient comparative concurrent Built-In Self-Test technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
62Wei-Lun Wang, Kuen-Jong Lee Accelerated test pattern generators for mixed-mode BIST environments. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
61Jason P. Hurst, Adit D. Singh A differential built-in current sensor design for high speed IDDQ testing. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
60Kentaroh Katoh, Hideo Ito Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
58Christian Dufaza Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF DOBIST, Test, Built-In Self Test
58Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
58Nilanjan Mukherjee, Ramesh Karri Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
58Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska Design and performance of CMOS TSPC cells for high speed pseudo random testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
58Jacob Savir On shrinking wide compressors. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
57Li Chen, Sujit Dey Software-based self-testing methodology for processor cores. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
57Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng Embedded hardware and software self-testing methodologies for processor cores. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
56Paul Chang, Brion L. Keller, Sarala Paliwal Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation
56Albrecht P. Stroele Arithmetic Pattern Generators for Built-In Self-Test. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Arithmetic functions, built-in self-test, design for testability, pattern generator
56Yervant Zorian, Hakim Bederr An Effective Multi-Chip BIST Scheme. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF built-in self-test, DFT, MCM testing
56Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
56T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael Faulty chip identification in a multi chip module system. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
56Manoj Franklin Fast computation of C-MISR signatures. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
56Joan Carletta, Christos A. Papachristou Testability analysis and insertion for RTL circuits based on pseudorandom BIST. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
56Michael Nicolaidis Self-exercising checkers for unified built-in self-test (UBIST). Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
54Wimol San-Um, Masayoshi Tachibana Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
54Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
52Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. Search on Bibsonomy J. Electronic Testing The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test
52Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy Built In Self Test for Ring Addressed FIFOs with Transparent Latches. Search on Bibsonomy MTDT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Built In Self Test, Memory testing, Embedded memories
52Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis An efficient built-in self test method for robust path delay fault testing. Search on Bibsonomy J. Electronic Testing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
52Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis A concurrent built-in self-test architecture based on a self-testing RAM. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Kewal K. Saluja On-chip testing of random access memories. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
51Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
50Y. Tsiatouhas, Th. Haniotakis A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Built-In Self Test, Delay Fault Testing
50Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF linear hybrid cellular automata, sequential fault, transition capability, built-in self-test, linear feedback shift register, linear finite state machine
50Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama Built-in self test for C-testable ILA's. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
50Markus Seuring Combining Scan Test and Built-in Self Test. Search on Bibsonomy J. Electronic Testing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF MBIST, BIST, scan test, production test, stress test
49Roberto Bevacqua, Luca Guerrazzi, Franco Fummi SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
48Gladys Omayra Ducoudray, Jaime Ramírez-Angulo Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF iDD analysis, built-in self-test, mixed-signal test
48Samir Boubezari, Bozena Kaminska A new reconfigurable Test Vector Generator for built-in self-test applications. Search on Bibsonomy J. Electronic Testing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF rank order clustering, built-in self-test, cellular automata, test vector generator
48Gary L. Craig, Charles R. Kime, Kewal K. Saluja Test Scheduling and Control for VLSI Built-In Self-Test. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF test resource sharing, suboptimum algorithms, equal length test, unequal length test, scheduling, VLSI, VLSI, built-in self-test, integrated circuit testing, BIST, automatic testing, hierarchical model, test scheduling, algorithm performance
47Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch An optimized BIST test pattern generator for delay testing. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
47S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch A new test pattern generation method for delay fault testing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
47Jung-Cheun Lien, Melvin A. Breuer Test program synthesis for modules and chips having boundary scan. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
46Janusz Rajski, Jerzy Tyszer Recursive Pseudoexhaustive Test Pattern Generation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF recursive pseudoexhaustive test pattern generation, parallel pattern generator, exclusive-or array, serial generators, scan-based built-in self-test, logic testing, built-in self test, test vectors, characteristic functions
46John Y. Sayah, Charles R. Kime Test Scheduling in High Performance VLSI System Implementations. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF high performance VLSI system, parallel test execution, organization level, test parallelism, schedulability criteria, suboptimum heuristic-based algorithms, VLSI, built-in self-test, built-in self test, time, integrated circuit testing, design for testability, automatic testing, space, heuristic programming, test scheduling, inherent parallelism
46Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF mutual checking, multiple signature testing, self loops, built-in self test, aliasing
46Albrecht P. Stroele, Hans-Joachim Wunderlich Test register insertion with minimum hardware cost. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test register insertion, BILBO, CBILBO, Built-in self-test
45Mohammad Tehranipoor, Reza M. Rad Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Lei Li, Zhanglei Wang, Krishnendu Chakrabarty Scan-BIST based on cluster analysis and the encoding of repeating sequences. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF clustering test data volume, Built-in self-test (BIST), test compression
45Ugur Kalay, Douglas V. Hall, Marek A. Perkowski A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
45Jing-Yang Jou An effective BIST design for PLA. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
45Jacob Savir Generator choices for delay test. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
43Saman Adham, Sanjay Gupta DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
43Da Wang, Yu Hu, Huawei Li, Xiaowei Li 0001 Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
43Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
43Wu-Tung Cheng Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
43Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer Estimation of BIST Resources During High-Level Synthesis. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF built-in self-test, high-level synthesis, estimation
43Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbauwhede Low Cost Built in Self Test for Public Key Crypto Cores. Search on Bibsonomy FDTC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Security, Built-In Self-Test, Public-Key Cryptography, Pseudorandom Testing
43Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. Search on Bibsonomy J. Electronic Testing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Analog built-in self-test, Transient response analysis, FPAA
43Sungbae Hwang, Jacob A. Abraham Selective-run built-in self-test using an embedded processor. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator
43Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An Effective Built-In Self-Test Scheme for Parallel Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF tree multipliers, Built-in self-test, array multipliers, cell fault model
43Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian Effective Built-In Self-Test for Booth Multipliers. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Booth multipliers, Built-In Self Test, design for testability, data paths
43T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian Built-In Self-Test with an Alternating Output. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF cover circuit, Built-in self-test, circuit testing
43Yuejian Wu, Sanjay Gupta Built-In Self-Test for Multi-Port RAMs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
43Sandeep K. Gupta, Dhiraj K. Pradhan Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF concurrent checking, fault-escape probability, parity prediction, Built-in self-test, BIST
43Kazuhiko Iwasaki, Shigeo Nakamura Aliasing Error for a Mask ROM Built-In Self-Test. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mask ROM, experimental faults analysis, Built-in self-test, aliasing probability, MISRs
43Samir Boubezari, Bozena Kaminska A Deterministic Built-In-Self-Test Generator Based on Cellular Automata Structures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1995 DBLP  DOI  BibTeX  RDF autonomous finite-state machine, built-in self-test, Cellular automata, programmable logic array, test vector generator
43Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky A Data Compression Technique for Built-In Self-Test. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF data compression technique, error-propagating space compression, Exclusive-NOR, logic testing, data compression, built-in self-test, BIST, automatic testing, self-testing, fault analysis, Exclusive-OR
43Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1987 DBLP  DOI  BibTeX  RDF output response compression, parity bits, Built-in self test (BIST), fault models, fault coverage, VLSI design, test pattern generation, programmable logic array (PLA)
43Rupsa Chakraborty, Dipanwita Roy Chowdhury coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips. Search on Bibsonomy ACRI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
43Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF output response compression, Built-in self-test, scan design
42Kanad Chakraborty Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
42Alex Orailoglu Microarchitectural synthesis for rapid BIST testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
42Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
41Xiaoding Chen, Michael S. Hsiao Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF built-in-self-test, System-on-a-chip, spectral analysis
41Debaleena Das, Mark G. Karpovsky Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF exhaustive codes, near-exhaustive codes, built-in self-test, memory testing, pattern sensitive faults
41Lei Chen 0010, Zhiquan Zhang, Zhiping Wen A novel BIST approach for testing input/output buffers in FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF i/o buffers, built-in self-test, fpga testing
40Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Dirk Niggemeyer, M. Rüffer Parametric Built-In Self-Test of VLSI Systems. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Benoit Provost, Edgar Sánchez-Sinencio, Anna Maria Brosa A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF NGCC amplifier, BIST, Fault-coverage, Analog testing, Time-domain
39Kay Suenaga, Rodrigo Picos, Sebastià A. Bota, Miquel Roca, Eugeni Isern, Eugenio García A Module for BiST of CMOS RF Receivers. Search on Bibsonomy J. Electronic Testing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF RF-IC, Test, Built-in-self-test, MOS, Mixers
39Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh BIST for Network-on-Chip Interconnect Infrastructures. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip
39Kumar L. Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen, Randall L. Geiger BIST and production testing of ADCs using imprecise stimulus. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF ADC linearity, imprecision measurement, imprecision stimulus, built-in self-test, Analog and mixed-signal testing, production test
39Gabriela Peretti, Eduardo Romero 0002, Franco Salvático, Carlos A. Marqués A Functional Approach to Test Cascaded BCD Counters. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF off-line built-in self-test, functional test, synchronous systems, digital testing
39Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston Effective diagnostics through interval unloads in a BIST environment. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF fault diagnosis, built-in self-test (BIST)
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