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Searching for phrase combinational circuits (changed automatically) with no syntactic query expansion in all metadata.

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article(285) inproceedings(501) phdthesis(1)
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Found 787 publication records. Showing 787 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
127Anand Raghunathan, Pranav Ashar, Sharad Malik Test generation for cyclic combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
103Marc D. Riedel, Jehoshua Bruck The synthesis of cyclic combinational circuits. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF feedback, logic synthesis, cycles, combinational logic
95Dhruva R. Chakrabarti, Ajai Jain An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
85Anand Raghunathan, Pranav Ashar, Sharad Malik Test generation for cyclic combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
85Sharad Malik Analysis of cyclic combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
75Xunwei Wu, Xiexiong Chen, Jizhong Shen Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF race-hazard, skip-hazard, multivalued combinational circuits, race hazards, AND/OR expression, skip hazard, multivalued circuits, fast transition, small load capacitor, combinational circuits, multivalued logic circuits, hazards and race conditions, input signals
72Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu Generation of tenacious tests for small gate delay faults in combinational circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
72Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey A simple technique for locating gate-level faults in combinational circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
69Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi Formal Verification Of Self-Testing Properties Of Combinational Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
69Sreejit Chakravarty, Yiming Gong Voting model based diagnosis of bridging faults in combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
69Abdel-Fattah Yousif, Jun Gu Concurrent automatic test pattern generation algorithm for combinational circuits. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF concurrent automatic test pattern generation algorithm, global computations techniques, concurrent search, ISCAS'85, ISCAS'89 benchmarks, computational complexity, logic testing, NP-hard, combinational circuits, combinational circuits, automatic testing
67Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song Transforming Cyclic Circuits Into Acyclic Equivalents. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen Equivalence checking of combinational circuits using Boolean expression diagrams. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
61Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff Soft Delay Error Effects in CMOS Combinational Circuits. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors
58Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal An efficient automatic test generation system for path delay faults in combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
58Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution
58S. A. Ali, G. Robert Redinbo Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF tight lower bounds, internal signal lines, fault diagnosis, logic testing, combinational circuits, combinational circuits, random testing, detection probabilities, single faults
57Emil Gizdarski, Hideo Fujiwara Spirit: satisfiability problem implementation for redundancy identification and test generation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
57Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak An improved output compaction technique for built-in self-test in VLSI circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
57Wuudiann Ke, Premachandran R. Menon Multifault testability of delay-testable circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
54Yong Je Lim, Mani Soma Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
53Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck Deterministic test generation for non-classical faults on the gate level. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
52Aiman H. El-Maleh, Yahya E. Osais Test vector decomposition-based static compaction algorithms for combinational circuits. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Static compaction, class-based clustering, independent fault clustering, test vector decomposition, taxonomy, combinational circuits
52Irith Pomeranz, Sudhakar M. Reddy Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF test generation, combinational circuits, stuck-at faults, logic simulation
52Irith Pomeranz, Sudhakar M. Reddy Functional test generation for delay faults in combinational circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
51Michiko Inoue, Emil Gizdarski, Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
50Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer Test generation for crosstalk-induced faults: framework and computational result. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF 2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
50Valery A. Vardanian On completely robust path delay fault testable realization of logic functions. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
50Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
50A. Pal, R. K. Gorai, V. V. S. S. Raju Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
50Enrico Macii, Massimo Poncino Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
50Angela Krstic, Kwang-Ting Cheng Generation of high quality tests for functional sensitizable paths. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information
48Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell Energy minimization and design for testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF neural networks, graph theory, energy minimization, digital testing, Combinational logic circuits
46Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang An efficient combinationality check technique for the synthesis of cyclic combinational circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Dirk W. Hoffmann, Thomas Kropf Efficient Design Error Correction of Digital Circuits. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
45Ramesh C. Tekumalla, Premachandran R. Menon Identification of primitive faults in combinational and sequentialcircuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Ilker Hamzaoglu, Janak H. Patel Test set compaction algorithms for combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
42Yung-Chih Chen, Chun-Yao Wang An Implicit Approach to Minimizing Range-Equivalent Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
42Irith Pomeranz, Sudhakar M. Reddy Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
42Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
41Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal Redundancy removal and test generation for circuits with non-Boolean primitives. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak Syndrome signature in output compaction for VLSI BIST. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
40Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Á. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro SET Fault Tolerant Combinational Circuits Based on Majority Logic. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester An efficient static algorithm for computing the soft error rates of combinational circuits. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Luís Guerra e Silva, Luís Miguel Silveira, João P. Marques Silva Algorithms for Solving Boolean Satisfiability in Combinational Circuits. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Circuit Delay Computation, Test Pattern Generation, Boolean Satisfiability, Circuit Satisfiability
40Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy Techniques for minimizing power dissipation in scan and combinational circuits during test application. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
40Ohyoung Song, Premachandran R. Menon Acceleration of trace-based fault simulation of combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
39Shiyi Xu, Wei Cen Forecasting the efficiency of test generation algorithms for digital circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
39Dimitrios Kagaris, Spyros Tragoudas Generating deterministic unordered test patterns with counters. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF counting circuits, deterministic unordered test patterns, counter-based schemes, built-in mechanisms, test pattern generation session, ISCAS'85 benchmarks, logic testing, built-in self test, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, hardware overhead
39C. P. Ravikumar, Hemant Joshi HISCOAP: a hierarchical testability analysis tool. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
39B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh A new methodology for the design of low-cost fail safe circuits and networks. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF low-cost fail safe circuits, safety critical electronic systems, input-output encoding problems, output encoding technique, low-cost design, systematic framework, graph theory, design methodology, encoding, combinational circuits, combinational circuits, graph embedding, graceful degradation, logic partitioning
39Dimitrios Karayiannis, Spyros Tragoudas Uniform area timing-driven circuit implementation. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
39Andrej Zemva, Franc Brglez Detectable perturbations: a paradigm for technology-specific multi-fault test generation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
39Wen Ching Wu, Chung-Len Lee, Jwu E. Chen Identification of robust untestable path delay faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
39Irith Pomeranz, Sudhakar M. Reddy Static compaction for two-pattern test sets. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
39Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton On breakable cyclic definitions. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana Fault equivalence identification in combinational circuits using implication and evaluation techniques. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton Approximate timing analysis of combinational circuits under the XBD0 model. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF delay computation, timing analysis, False path
39Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer SWiTEST: a switch level test generation system for CMOS combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
39Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004 IR-drop Reduction Through Combinational Circuit Partitioning. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Static Timing Analysis, IR-drop, circuit partitioning
39Soumitra Bose, Vishwani D. Agrawal Sequential logic path delay test generation by symbolic analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
39Yu-Shiang Lin, Dennis Sylvester Runtime leakage power estimation technique for combinational circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
39Irith Pomeranz, Sudhakar M. Reddy A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF test generation, Combinational circuits, genetic optimization
39Vishwani D. Agrawal, David Lee Characteristic polynomial method for verification and test of combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF combinational circuit test, randomly selected integers, input variables, integer-valued transform functions, fixed domain, multiple samples, randomly selected real numbers, output logic, logic testing, probability, Boolean functions, Boolean functions, combinational circuits, polynomials, error probability, characteristic polynomial
39Alessandro Bogliolo, Maurizio Damiani Synthesis of combinational circuits with special fault-handling capabilitie. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits
39Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya Logical redundancies in irredundant combinational circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
39Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF minimum test sets, monotone combinational circuits, minimum complete test set, monotone PLAs, computational complexity, complexity, logic testing, NP-complete, logic arrays, combinatorial circuits, literals
39Bhargab B. Bhattacharya, Sharad C. Seth Design of Parity Testable Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF parity testable combinational circuits, maximal supergates, single external test-mode pin, logic testing, integrated circuit testing, design for testability, integrated logic circuits, combinatorial circuits
39A. R. Virupakshia, V. C. V. Pratapa Reddy A Simple Random Test Procedure for Detecion of Single Intermittent Fault in Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF intermittent fault detection, Combinational circuits, random testing
39Miron Abramovici A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF single and multiple stuck-at faults, effect?cause analysis, module-level circuits, path-oriented approach, fault diagnosis, Combinational circuits, hierarchical approach
39Ronald L. Rivest The Necessity of Feedback in Minimal Monotone Combinational Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1977 DBLP  DOI  BibTeX  RDF gate complexity, minimal combinational circuits, Boolean functions, feedback, monotone functions
38Mandar Waghmode, Zhuo Li 0001, Weiping Shi Buffer insertion in large circuits with constructive solution search techniques. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF physical design, buffer insertion, cost optimization, interconnect synthesis
38Wolfgang Kunz, Dhiraj K. Pradhan Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
38Vesselin K. Vassilev, Julian F. Miller Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs. Search on Bibsonomy Evolvable Hardware The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Yen-Chun Lin, Chao-Cheng Shih A New Class of Depth-Size Optimal Parallel Prefix Circuits. Search on Bibsonomy The Journal of Supercomputing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF depth-size optimal, unbounded fan-out, VLSI, Combinational circuits, parallel prefix
37El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny On the generation of test patterns for multiple faults. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
37Walter Dosch Designing Combinational Circuits with List Homomorphisms. Search on Bibsonomy SERA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF functional hardware description, list homomorphism, iterative network, parity generator, priority resolution, High-level synthesis, comparator, tree network
37Fatih Kocan, Daniel G. Saab ATPG for combinational circuits on configurable hardware. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Ramzi Ben Salah, Marius Bozga, Oded Maler On Timing Analysis of Combinational Circuits. Search on Bibsonomy FORMATS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Byungwoo Choi, D. M. H. Walker Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
36Vijay Sundararajan, Keshab K. Parhi Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
36Zhide Zeng, Jihua Chen, Hefeng Cao Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF finite backtracking test pattern generation, n to 1 tightly coupled integration mode, parallel-pattern, single-fault propagation, ultra large scale combinational circuit (ULSCC
35Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto Single-Event Upset Analysis and Protection in High Speed Circuits. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton Redundancies and don't cares in sequential logic synthesis. Search on Bibsonomy J. Electronic Testing The full citation details ... 1990 DBLP  DOI  BibTeX  RDF redundancies, synthesis for testability, don't cares
35Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. Search on Bibsonomy J. Electronic Testing The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
35Rajesh Garg, Charu Nagpal, Sunil P. Khatri A fast, analytical estimator for the SEU-induced pulse width in combinational designs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF single event upset (SEU), model, analysis
35Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Srimat T. Chakradhar, Anand Raghunathan Bottleneck removal algorithm for dynamic compaction in sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
34Dirk W. Hoffmann, Thomas Kropf Automatic Error Correction of Tri-State Circuits. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Automatic error correction, tri-states, fault diagnosis, BDDs, equivalence checking
34Hans-Georg Breunig The Complexity of Membership Problems for Circuits over Sets of Positive Numbers. Search on Bibsonomy FCT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Computational complexity, Combinational circuits, Arithmetic circuits
34Ilker Hamzaoglu, Janak H. Patel Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
34Aarti Gupta, Pranav Ashar Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
33Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns Leakage and leakage sensitivity computation for combinational circuits. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF iddq analysis, sensitivity, power estimation, leakage power
33Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Chandramouli Gopalakrishnan, Srinivas Katkoori Power Optimization of Combinational Circuits by Input Transformations. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Irith Pomeranz, Sudhakar M. Reddy Functional test generation for delay faults in combinational circuits. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
33V. V. Saposhnikov, Andrej A. Morosov, Vl. V. Saposhnikov, Michael Gössel A New Design Method for Self-Checking Unidirectional Combinational Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Irith Pomeranz, Sudhakar M. Reddy Design-for-testability for path delay faults in large combinational circuits using test points. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Hoon Choi, Seung Ho Hwang Improving the accuracy of support-set finding method for power estimation of combinational circuits. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
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